Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if noise couples to my timing clock edge? Will my display always look this good across manufacturing process corners? Is there enough timing margin to add spread spectrum (SS) for reduced electromagnetic interference (EMI)?
This article helps answer these questions by exploring the theoretical means for budgeting system timing. It also outlines empirical methods for creating and verifying timing margin using features of advanced programmable clocks.
Every digital electronic system requires a periodic signal or clock to initiate input data acquisition, data processing steps, and output data transmission. The input and output data can be represented by analog or digital signals, depending on which portions of the system are interfacing to the analog world or to another digital system.
When interfacing to the analog world, the system must have clock signals for the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) used at the inputs and outputs. Timing error of the sampling clocks used in ADCs and DACs results in data distortion. The analysis of analog data distortion is also critical to proper system operation, but here we’ll focus on the system timing associated with the transmission and processing of digital data.
The interfaces to digital systems require clocks to synchronize the transmission and receipt of data. When processing digital data, a clock is required to change the address pointers of the execution code and sequence data flow through the processing logic. A poor clock signal will create data-processing and/or datatransmission errors. Therefore, it’s necessary to carefully analyze the system timing requirements and select the proper timing components.
The traditional analysis method includes digital simulation of the toplevel system schematic using digital models of the subcomponents. However, this methodology doesn’t accurately model the effects of supply noise, coupled noise, actual timing generator characteristics, or advanced timing features like spread spectrum, which is used for EMI reduction.
To account for these effects, the system can be simulated at a frequency higher than the normal operating frequency to try and build in timing margin. However, the frequency delta is usually empirically determined from previous designs that worked with unknown margin plus some safety factor thrown in. Therefore, the resulting system is subject to timing failure within normal process distributions, in addition to unneeded cost increases for higher performance components than may actually be required.
A properly designed system uses timing references and distribution techniques that are accurate enough to ensure robust operation at all manufacturing corners without adding excessive cost. The cost analysis includes both the monetary cost of more accurate components and the expense of burning more power. Burning more power is an obvious issue for battery-powered systems, but it is also important for plug-in systems due to the incremental cost for increased capacity of the power supply and cooling components.
An extreme, brute-force example of maximizing timing margin in a system would be to use expensive third overtone crystal oscillators with differential 50-O outputs for each frequency on a board having six or more layers. This will shield the clock traces from noise and reduce EMI. Fortunately, the requirement for this level of timing accuracy and expense is extremely rare.
Making the accuracy versus cost tradeoff requires precise budgeting of the timing error from various sources. However, all too often, the inaccuracy of the timing models that are used in budgeting is only discovered during production. This subjects the program to a potential “lines down” situation when yields drop to unacceptable levels as a result of normal variations in components and process. If the timing margin could be verified during system development, the cost and performance can be optimized without compromising manufacturing yield.
A TYPICAL CASE
The typical elements of a timing budget as well as sources of timing error for a system that’s transmitting data between two components clocked by two copies of the same reference clock are listed in Table 1. These represent the items that must be considered in a system transferring data from a transmitter (XMTR) to a receiver (RCVR). Because most of the noise is correlated, each error item in the table must be added directly rather than using an rms value to arrive at the minimum period for the system clock.
The table assumes that one or both of the components use an internal clock multiplying phase-locked loop (PLL) to operate at higher internal rates than the externally applied reference clock. Systems with these types of components require special attention, since this can result in additional timing error.
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The bandwidth of the component PLL or different PLL bandwidths in two different components will track the reference clock jitter or spread-spectrum modulation differently. One way to think of this error, in the time domain, is as a delayed clock edge of a PLL that’s trying to follow changes in the system reference clock. Because the component’s internally multiplied clock may be used as the component’s input or output data strobe, this timing delay must be included in the data-transmission timing-error budget.
Based on Table 1, a system running at 250 MHz (1/4 ns) is reduced to 200 MHz (1/5 ns) due to timing errors. And before system-timing adjustments are made, even 250-MHz operation is marginal, depending on component and trace matching variations. Since the system is marginal, it may pass during prototyping or initial system validation, but fail during production.
Using the signal-integrity tuning features of an advanced programmable clock, the budgeted amount for several of these timing errors can be reduced. In addition, the confidence in sufficient timing margin can be increased by artificially introducing errors to validate the error modeling.
One example of a programmable clock generator that provides programmable optimization is the EPro clock from SpectraLinear. The various members of the EPro (Electrically Programmable) clock family incorporate from one to four low-power PLLs with up to 2048 nonvolatile control bits.
One of these clocks, the SL15300, allows fine-tuning of the output impedance (drive strength), output skew, operating frequency, and SS profile to minimize the timing errors as well as validate the amount needed for system timing margin. The PLLs can be programmed to consume less than 2 mA each. In addition, the program can be stored in internal nonvolatile memory or configured in real time through a twopin IIC port (Fig. 1). Table 2 summarizes the programmable capability of the SL15300.
The “After value” column in Table 1 shows that the programmable output impedance has been used to offset the load mismatch. Furthermore, the programmable skew minimizes the clock launch skew and offsets the systematic board trace mismatch. These parameters can’t be reduced to zero due to variations over process corners and the resolution of the programmable clock adjustment.
If further improvement is needed in the timing budget, the outputs can be programmed to be 180° out of phase, supporting the complementary HSTL (High Speed Transceiver Logic) format. In this case, most of the edge uncertainty due to noise is eliminated. That’s because the complementary traces are routed adjacent to each other and the complementary receiver rejects the induced common-mode noise.
The programmable features can also be used to determine system response to intentional timing errors. This debug tool is effective during development for measuring sensitivity of the system to various timing parameters.
In addition, the maximum frequency limit of the system can be determined by programming a specific part to have maximum timing-error deltas instead of the nominal values. This is accomplished by setting the skew, Tr/Tf, period, spread-spectrum magnitude, etc., to be equal to the maximum value allowed by the datasheet specification. Then the operating frequency can be incrementally programmed higher to the point of failure.
The last successful frequency is the maximum system frequency except for any production variation in the XMTR and RCVR devices. Production variations in the XMTR and RCVR timing can also be factored in by measuring the propagation and setup timing performance of those specific devices and using the difference between the measured and specified values to derate the measured maximum frequency.
Running a particular board at the highest operating frequency also allows various timing sensitivities to be examined. For example, if the maximum operating frequency is measured to be 222 MHz, then the spread-spectrum modulation amplitude is doubled and the new maximum frequency is found to be 217 MHz. Then we know that doubling the spread amplitude resulted in an additional 100 ps of tracking error (= 1/217 MHz – 1/222 MHz).
For the above example, the XMTR and RCVR timing parameters can’t be artificially increased to their worstcase values. Therefore, the difference between their measured values and worst-case specifications can be manually added to the minimum clock period to ensure the system will accommodate the process variations of future shipments. For additional safety margin, the timing component can be programmed in real time during production test to run at a frequency higher than nominal. This ensures that each system has adequate timing margin and will have no timing issues in the field.
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Other examples of using a programmable clock to validate system timing or save power include programming the PLL to operate with higher or lower long-term jitter (LTJ). LTJ is the variation in time between clock edges separated by N clock cycles. A common value for N is 1000. Figure 2 shows the same output of the SL15300 programmed for two different LTJ extremes. It’s particularly important for clocks used as video references to avoid “wavy” displays and those used to clock transceiver components (e.g., USB and LAN transceivers) to maximize the eye diagram opening.
Higher LTJ is achieved by lowering the phase-detector rate, bandwidth, and/ or voltage-controlled oscillator (VCO) frequency of the PLL. It’s useful during development to ensure the system has sufficient timing margin. LTJ can then be reduced to the point where all specifications will be met over process corners while consuming minimum power. When power isn’t a primary concern, the longterm jitter can be reduced to the lowest value allowed by the clock technology to maximize system timing margin.
In summary, the timing sensitivities of digital systems aren’t well modeled. Thus, programmable clocks can be used to maximize and validate timing margin during development and ensure timing margin during production. This optimization helps reduce system cost and optimize system performance, including power dissipation.