The highly integrated Si5324 clock IC from Silicon Laboratories is optimized for professional broadcast video applications. It replaces traditional multi-component video phase-locked loop (PLL) solutions with a single clock IC while providing 80% less jitter than competing solutions. It also can generate virtually any output frequency from 2 kHz to 1.4 GHz from any input frequency ranging from 2 kHz to 710 MHz, simplifying synchronization in next-generation multi-rate video equipment. The Si5324 is ideal for video capture, conversion, editing, display, and distribution equipment that must be synchronized within video studios.
Clock generation and synchronization have become increasingly complex in broadcast video applications due to the proliferation in the number of HD video formats and frame rates that must be supported. One solution is the process known as genlock, which synchronizes all video equipment to a common sync source, though it has been challenging.
Additionally, the industry’s migration to high-speed 3G-SDI requires improved jitter performance in comparison to legacy video standards, increasing the design challenge for equipment makers. 3G-SDI is a serial digital interface standard of the ITU and the Society of Motion Picture and Television Engineers (SMPTE). Used to transmit uncompressed digital video over 75-Ω coax cable within studios, it’s a standard feature of most modern video equipment. HD-SDI uses a basic rate of 1.485 Gbits/s, but the latest version called SMPTE 424M specifies a data rate of 2.97 Gbits/s.
Traditional genlock solutions require discrete voltage-controlled crystal oscillator (VCXO) and filter components and generally support a limited range of input/output frequencies. Most suffer from relatively poor jitter performance that isn’t up to 3G-SDI requirements. One way to address the jitter problem is to consider using the Si5324 for gunlock.
The Si5324’s jitter performance of 5 ps p-p provides significant margin to all existing and emerging video standards, including 3G-SDI (SMPTE 424M). By meeting these standards with considerable margin, the jitter budget that would otherwise be allocated to clock generation can be applied to other components in the system, simplifying component selection and design.
The IC incorporates all PLL components into a single highly integrated device, eliminating the need for multiple PLL ICs, external filters, and VCXO components (see the figure). Based on Silicon Labs’ patented DSPLL technology, the Si5324’s fully integrated, digitally programmable loop filter supports loop bandwidths ranging from 4 to 525 Hz as well as a low-phase-noise internal voltage-controlled oscillator (VCO). Programmable dividers make it possible for the Si5324 to generate and synchronize all common HD video and audio reference frequencies without any component changes, allowing one design for multiple applications and simplifying design reuse.
Silicon Labs also offers XOs and VCXOs to use with the Si5324 in broadcast video applications. Its Si590/591/595 family of XO/VCXOs provides any frequency from 10 to 525 MHz, any format (CMOS, LVDS, LVPECL, CML), and any supply voltage (1.8, 2.5, or 3.3 V), with guaranteed low jitter of 1 ps rms (max).
The Si5324 is packaged in a 36-lead, 6- by 6-mm quad flat no-lead (QFN) package, with samples and production quantities available now. It costs $17.95 to $57.20, depending on the selected output clock frequency range (A/B/C/D speed grades) in 1000-unit quantities. The Si590/591/595 XO/VCXOs are available now in an industry-standard 5- by 7-mm package. The Si590/591 XOs cost between $4.08 and $8.50 in 10,000-unit quantities, depending on frequency and stability. The Si595 VCXO costs between $4.89 and $11.48 in 10,000-unit quantities, depending on frequency and stability.