The world of IC and system design sees process technologies and system architectures come and go at mach speed. The tools designers require to keep pace change just as quickly. For those who simply must stay abreast or else, the 41st Design Automation Conference (San Diego, June 7-11) is the place to get on top of the trends in tools, methodologies, and technologies. More than 10,000 attendees are expected to peruse the offerings of over 170 exhibitors.
This year's technical program includes seven tracks: business; system-level design and verification; power; logic design and test; embedded systems; nanometer analysis and simulation; and physical circuit design. Attendees will be able to choose from over 200 panels, papers, sessions, workshops, and tutorials.
But for users of EDA software and associated hardware, there always are multiple reasons to make the annual pilgrimage to DAC. The technical sessions go hand in hand with the activities on the show floor and in the maze of fortress-like demonstration suites. The sessions get you up to speed on the latest technologies and methodologies. But there's nothing like seeing them in action, bringing the theoretical into practical reality.
DAC is often a show where one can watch industry trends coalesce. One nascent trend over the past few years is the move to a level of abstraction higher than register-transfer level (RTL). In San Diego, a number of established EDA vendors and startups will display the latest in electronic-system-level (ESL) tools and methodologies.
Summit Design is among the more established ESL houses. Version 4.0 of its flagship Visual Elite tool now offers built-in SystemC native constructs that accelerate modeling and verification, making it intuitive for hardware designers as well as for C/C++ coders. The tool offers visibility into SystemC code from both hardware and software perspectives (Fig. 1). A Design introspection view is hardware-centric, while a Code introspection view offers a C/C++ look at the language structure. Transaction-level verification tools also were added. Prices start from $15,000.
Another ESL stalwart, CoWare, will show the latest release of its ConvergenSC ESL design platform, which combines new hardware/software partitioning capabilities with platform-assembly features. Also in the CoWare stable is the LISATek tool. It enables embedded processor designers to automatically model their work at a high level of abstraction, as well as generate instruction-set simulators and a complete set of associated software tools (including a custom C compiler).
Debug continues to evolve, spreading in its influence to cover all phases of the design cycle. Novas Software will divulge an expanded strategy/roadmap to address advanced debug and system-on-a-chip (SoC) development beyond the traditional definition of hardware debug. Novas is building upon its existing core debug foundation to provide a platform that spans the full design cycle.
Some new capabilities Novas will show include support for standard communications/bus protocols with additional transaction-level interfaces that target ESL requirements. The company will unveil a suite of design-analysis tools, including the production release of the Verdi post-simulation assertion checker along with new visualization enhancements. There also will be links from Novas' debug systems to physical layout tools.
Celoxica's DAC booth will feature the first public showing of the company's safety and security demonstrators built using BAE Systems' and Celoxica's technology and RC series development platforms. A prototype fingerprint-matching engine based on BAE Systems' LEARNN neural-network algorithm processing technology will be running on a Celoxica RC200 development board. The LEARNN technology is implemented in programmable logic using Celoxica's C-to-FPGA synthesis tools.
Implementing DSP functionality on FPGAs has become quite a popular trend. AccelChip's DSP Synthesis tool gives users of the MathWorks' Matlab algorithm-based design environment a direct path to silicon, automatically generating synthesizable RTL from Matlab algorithms (Fig. 2). Building on its earlier AccelFPGA tool, AccelChip's DSP Synthesis tool supports FPGAs, ASICs, and structured ASICs. It also works in enhanced flows with the MathWorks' Simulink and Xilinx's ISE and System Generator tools.
DSP Synthesis generates cycle-accurate models for Simulink and other DSP-based component integration environments. In so doing, it enables system-level verification of all components using libraries and math-based models. It also exports models that are verified against the golden Matlab source code into Simulink.
The long-awaited formal announcement of Forte Design Systems' Cynthesizer finally comes at this year's DAC. Cynthesizer is touted as the first behavioral synthesis tool to offer a direct implementation path from SystemC to RTL, verification, and cosimulation. It automatically generates optimized RTL from a C++/SystemC algorithmic design description.
Using untimed C models, Cynthesizer builds a fully timed RTL hardware implementation based on the designer's constraints. It outputs industry-standard RTL specifically targeted for a number of downstream flows and tools. Cynthesizer's behavioral synthesis functionality includes automation of tasks such as operation scheduling, cycle timing, control, and datapath design and resource allocation. Pricing is still being determined.
Arteris, a startup gearing up to deliver its network-on-chip (NoC) technology in the form of IP and high-level design tools, will have a low-profile presence at DAC. To address the challenges of on-chip interconnections and communications, the company plans to offer high-level-flow, EDA-style tools and capabilities for NoC architectural analysis and design exploration (i.e., system-level language capture, synthesis, and simulation). With such tools, designers can use languages like SystemC and SystemVerilog to model the network, drive the tools, and explore options for implementation.
These days, more designers are at least interested in beginning the design process at a level of abstraction higher than RTL. It's a good thing, because all designs must eventually pass through the RT level in their journey toward implementation. In the traditional "front end" of the process, much DAC activity surrounds new products and technologies.
Optimizing between conflicting design goals—such as die size, power, leakage, speed, yield, and cost—is a neverending issue for engineers. Designers need a fast yet accurate means of comparing and visualizing tradeoffs in library characteristics, semiconductor process nodes, memory configurations, and IP. Giga Scale IC's InCyte gives them a specification cockpit, estimation engine, floorplan generator, performance calculator, and comparison display, driven by Giga Scale IC's Technology Macro Modeler. Bundled with a portfolio of libraries (from 90 nm to 0.35 µm) and a broad family of hard and soft IP macros, users can gain insight into available offerings from semiconductor vendors.
InCyte-Specify, designed for estimation and architectural optimization, captures and optimizes the initial chip specification. It's priced at $6000 per year. InCyte-Create, targeted at the chip creation and implementation process, costs from $15,000 per year.
Designers of math-intensive chips for 3D graphics and other applications may want to look at Arithmatica's CellMath line of IP for standard-cell and custom IC design flows. When applied to math-critical blocks in graphics chips, CellMath IP can reduce overall chip area by up to 10% while boosting processing performance.
The CellMath line includes a graphics library, processor library, and configurable instances, all of which form a rich set of application-level functions in billions of permutations. The IP is delivered with gate-level netlists and bit-accurate simulation models. Functions can be tailored for bit widths, speed and area goals, pipelining, and more. Pricing starts at $175,000.
FPGA designers, like their ASIC counterparts, need static timing analysis to find problems before place and route. Hier Design's TimeAhead offers FPGA designers fast feedback on potential timing bottlenecks, enabling them to make early floor-plan adjustments. The timing-analysis environment is tight-ly integrated with Hier's PlanAhead hierarchical floorplanner and its schematic, netlist, and floorplan views. Thus, TimeAhead gives users cross-highlighting from the analysis report to critical paths graphically traced within the floorplan (Fig. 3). PlanAhead and TimeAhead are now sold together as a package, with a time-based license costing $40,000 per year.
Beach Solutions will use DAC to launch Version 3.2 of its EASI-Studio. This tool provides a structured approach to capturing and maintaining design specification data in one place and then validating the data against customizable design and interface rules. Version 3.2 can "watermark" design data as reliable once it's checked and validated.
Aptix and SoftRISC will present the results of a collaborative effort, their voice-over-IP development and prototyping environment based on the ARM PrimeXsys platform. The environment consists of an Aptix System Explorer prototyping environment integrated with SoftRISC VoIP application software. Available in the second quarter, the Aptix environment starts at $80,000, while the SoftRISC software components start at $75,000.
Zenasis Technologies will have two major announcements at DAC. First is version 2.1 of its flagship ZenTime product, a cell-based timing optimization tool that identifies and combines standard cells in critical timing paths and then replaces them with design-specific custom cells. The tool straddles the front and back ends of the design cycle. New features include a three- to four-time increase in runtime speed.
Second, Zenasis' ZenCell Factory 1.1 complements ZenTime. This automated library-cell generation engine can create, layout, characterize, and verify hundreds of combinational logic cells in a matter of days. It can function in standalone fashion or be seamlessly integrated with ZenTime and other tools in an ASIC flow. ZenCell Factory is priced for term-based licensing at $95,000 per year. It runs on Linux and Sun-Solaris platforms.
Another stealth launch in the mold of Forte Design comes via FishTail Design Automation. FishTail's Focus tool takes synthesizable RTL and clock definitions as inputs and automatically generates the design's false and multicycle paths. The resulting "golden" timing constraints, arrived at before the outset of physical implementation, should enable designers to reach timing closure much more quickly. Focus goes for $90,000 per seat per year.
Tool interoperability is a subject of interest to designers in all phases of the design cycle. The Silicon Integration Initiative's OpenAccess Coalition will show a new Verilog reader/writer kit that was jointly developed by Hewlett-Packard and Cadence. The kit is now available for download at www.openeda.si2.org. It lets designers exchange netlist information directly with the OpenAccess design database.
At DAC, the OpenAccess Coalition also expects to deliver the beta release of its OpenAccess 2.2 code. This release of the reference database will offer performance enhancements as well as improved support for a new region-query application programming interface, rules and constraints, data-management changes, and more.
The subset of EDA tools for analog designers will see some interesting activity at DAC. More analog tools are appearing, though it remains to be seen whether analog designers will become more accepting of them.
Anasift Technology will exhibit its AMPSO v1.2 analog optimization tool, which is meant for linear amplification circuits such as op amps, analog buffers, comparators, bandgap references, voltage regulators, and others. Inputs to the tool include Spice netlists, model libraries, design requirements, and optimization corners. This tool optimizes and sizes circuits to meet design specifications across all optimization corners. It outputs designs in pure text format and exports the optimized results to users' existing analog design flow.
Designers of high-voltage ICs like LCD and thin-film transistor (TFT) drivers, power-management ICs, motor controllers, and others have specific needs not addressed by many EDA tools. Silvaco's tool suite is intended to fill that gap. At the front end, the Scholar schematic editor drives the SmartSpice circuit simulator, Expert layout editor, and Guardian DRC/LVS/LPE tools. The suite supports legacy models and netlists from other simulators, as well as the Verilog-A language for compact device models and analog behavioral models. A front-end seat of Scholar and SmartSpice starts at $35,000 for a perpetual license.
Accurate simulation is a must in the analog world. To that end, Ansoft's Nexxim simulator runs frequency- and time-domain analyses using the same circuit netlist and library models, ensuring consistent results from the two different domains. Nexxim offers a dynamic parametrized link to Ansoft's HFSS 3D electromagnetic simulation tool and its Q3D parasitic extraction engine. It also performs cosimulation with Ansoft Designer's Solver on Demand planar electromagnetic and system simulators. Nexxim will be available in the second quarter.
The latest version of Applied Wave Research's Analog Office will be on display at the show. Analog Office 2004, a full analog design environment that spans the entire flow down through circuit-level design and verification, now supports the Linux operating system. It's been enhanced to handle arbitrary layout geometries as well as automatic and on-the-fly connectivity extraction in layout. It also now supports the Verilog-A analog behavioral language. Time-based licenses range from $8000 to $40,000. Delivery begins in the third quarter.
Few subjects in EDA draw more interest or attention than verification. It's still the "mother of all bottlenecks." At DAC, advances in various verification technologies will include assertion-based verification and hardware-assisted verification.
Verisity will show its SpeXsim product, which integrates its flagship Specman Elite testbench automation tool with its Xsim simulator. SpeXsim also will be tightly integrated with the SureCov code-coverage tool. On top of that, the package links Verisity's process automation technologies with the scalable infrastructure technologies recently acquired from Axis Systems.
SpeXsim supports every current and proposed IEEE design automation standard, including VHDL, Verilog, SystemC, and the emerging IEEE P1647 verification language based on Verisity's e language. It'll be available for Solaris and Red Hat Linux in the third quarter. Pricing is $33,000 for a time-based license and maintenance.
An addition to 0-In Design Automation's Archer verification system will automate verification of all possible clock-domain-crossing (CDC) metastability effects in SoCs and ASICs. The CDC-FX enhancement lets designers determine whether jitter in signals crossing clock domains may cause functional defects in their RTL code. The tool automatically inserts a metastability-effects generator into the RTL code and uses formal techniques to analyze all possible errors. CDC-FX is a $50,000 option to the Archer system. It will ship in the third quarter.
Major updates to @HDL's products will be featured at DAC. Version 4.0 of @Verifier and @Designer were updated to improve the productivity of design and verification teams working with the assertion languages represented by Accellera's PSL and SystemVerilog.
The company added what it calls Assertion Studio technology, which includes five major components to enhance use of assertions. Among them is Assertion Visualizer. It reads in assertions written in either PSL or SystemVerilog and then automatically creates the equivalent timing diagram for the assertion sequence. This and other enhancements combine to make it easier than ever to adopt assertion-based verification.
Tharas Systems will bring its latest Hammer hardware-assisted simulation accelerator to the show. The Hammer 100 sports an architecture that compiles Verilog, VHDL, or mixed-language designs at 20 million to 50 million RTL gate equivalents per hour on a single workstation. It has a capacity of up to 128 million RTL equivalent gates and runs twice as fast as the earlier Hammer 50 accelerator. Also, it includes up to 16 Gbytes of memory.
A concurrent waveform conversion capability slashes time-to-waveforms by compressing trace data and concurrently converting that data into waveforms for display. A parallel waveform capability permits conversion of compressed simulation trace data dumps across a network of paralleled workstations. A progressive waveform converter can be used during active debug sessions, allowing users to save relevant trace data only if and when simulation fails or doesn't meet expectations. A base 32-Mgate system costs about $850,000.
With ever-deepening submicron silicon processes comes a host of design issues that require intensive analysis capabilities. Sequence Design will show an upgrade to its PhysicalStudio tool. Thanks to a partnership with Golden Gate Technology, Sequence added engineering-change-order (ECO) routing to Physical Studio as well as capabilities that enable users to modify power without impacting timing or signal integrity. A one-year license starts at $220,000.
ReShape's PD Builder, a tool that captures design-flow knowledge to enhance reusability, has been added to Open Flowlib. Flowlib provides a multivendor reference design flow that embodies expert know-how for tools from various vendors. Tool expertise is captured in modular work units as "stages," which can be placement, routing, or others. PD Builder uses the data from Open Flowlib to automatically create custom scripts for each stage in context of the full chip.
At DAC, Apache Design Solutions will unveil enhancements to its RedHawk-SDL physical power integrity tool. RedHawk-SDL can now identify additional dynamic power issues, including multiple voltage-threshold transistors, multiple VDD designs, header switches/power gates, and transient simulation of power toggling. It supports multiple levels of timing analysis from instance level to chip level.
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