Electronic Design

DAC Gets Wild And Crazy

Some of the Design Automation Conference's party spirit makes its way into the technical program at this year's show.

Like many niches in the electronics industry, EDA has a bit of a split personality. By day, it's typically all about algorithms, languages, standards, and myriad other aspects of putting together cohesive design and verification flows. But EDA also has its wild side, which is most visibly displayed at the annual Design Automation Conference (DAC).

This year's 44th DAC (San Diego, June 4-8) will be no different. As night falls and the show floor goes dark, ties are loosened, hair is let down, the music gets loud, and the parties crank up to a fever pitch. Mixing some of that "party-animal" attitude with its relentless hunt for the Next Big Thing, DAC's technical program includes a Tuesday special session titled "Wild And Crazy Ideas" (WACI). The session will tackle some thought-provoking notions that are less incremental and more revolutionary.

The conference as a whole explores some emerging trends in EDA that show promise in terms of growth. One that stands out is automotive electronics (see "DAC Goes On The Road,").

As always, DAC attendees will be able to roam the show floor with its booths and integrated demo suites. There, they can peruse the vendors' offerings in any and all areas related to EDA.

ESL: FROM THE TOP
Continually evolving electronic system-level (ESL) flows help to facilitate transaction-level modeling (TLM) work for early architectural exploration. At DAC, Bluespec and EVE will team to show an integrated platform for ESL verification, modeling, and architectural design.

The pairing of EVE's ZeBu hardware-assisted verification platforms and Bluespec's ESL synthesis tools results in a single development environment for models, transactors, implementations, and synthesizable verification testbenches, as well as a rich foundation library of intellectual property (IP). With the speed of EVE's FPGA-based environment, Bluespec's synthesizable transactors and models enable a seamless, heterogeneous mix of models, implementations, a verification testbench, and software models connected through transactors (Fig. 1).

CoWare plans to show the latest release of its platform-driven ESL environment for hardware designers, plus the integration of that platform with its Virtual Platform Product Family for software developers.

The latest release of the Virtual Platform Product Family addresses challenges associated with software development for multicore platform-based design. New features include automated packaging and licensing of a binary executable virtual hardware platform, which can be distributed across the enterprise and to partners and customers. The CoWare Virtual Platform Product Family starts at $10,000 U.S. list, based on the configuration.

Low-power design is on almost everyone's minds these days, even in the rarefied ESL domain. ChipVision Design Systems will exhibit ESL technology that lets RTL designers work interactively with system-level descriptions to generate power-optimized RTL code. It creates implementation tradeoff options for RTL designers and immediately and accurately implements their visualized choices (Fig. 2).

The company claims that using this technology at the system level to analyze power results in 75% pre-RTL energy savings; shortens time-to-results by a factor of 60; and creates code that's nine times more compact.

Yet another offering at DAC aims at visually oriented architectural development. Version 2.1 of CoFluent Design's CoFluent Studio enables performance analysis of complex hardware/software systems through a unique mapping technology. With it, explicit and dynamic specifications can be decided on early in the process.

FRONT-END DESIGN
RTL has become a more or less commoditized area. Yet there's always room for incremental improvements in RTL. Chip Estimate's InCyte chip-planning system now predicts chip performance along with accurate estimation of die area, power, and packaged chip cost. This arms users with feedback on the feasibility of achieving performance targets, along with die area, power, and packaged chip cost. InCyte starts at $35,000/per year.

In addition, more than 20 IP suppliers will present the latest news about IP in the Chip Estimate booth. Visitors to the booth can also put together a chip plan in less than 15 minutes and leave DAC with a spec, a plan, and a report.

IC design is truly a global affair, with collaborators, vendors, and support coming from all corners of the planet. IC Manage will show its GDP (Global Design Platform), a data-management system that offers design assembly, derivative management, and real-time worldwide delivery.

THE VERIFICATION FRONT
A longstanding concern for many designers is the absence of objective quality assurance in systems-on-a-chip (SoCs) and blocks of intellectual property (IP). Certess Inc. will unveil the Certitude product, which it terms a "functional qualification" tool. Certess' patented mutation-analysis technology objectively analyzes, measures, and enables the improvement of functional-verification environments for complex designs. Pricing starts at $100,000 for a one-year time-based license.

OneSpin Solutions GmbH will show an enhancement of its flagship OneSpin 360 Module Verifier (360 MV) software. The tool simultaneously verifies multiple configurations that can be generated from a configurable IP block, significantly reducing the time, effort, and cost incurred by multiple, individual verifications. The enhanced 360 MV supports the verification of IP with configurable functionality (Fig. 3).

On the broader verification front, Cadence Design Systems will arrive at DAC with an upgrade to its Virtuoso multimode simulator (MMSIM). Version 6.2 includes improvements to the common infrastructure supporting multimode functionality. In this way, Cadence hopes to address the risks and cost inherent in full-system integration.

A common, fully integrated database of netlists and models lets MMSIM v6.2 simulate analog, RF, memory, and mixed-signal designs and design blocks (Fig. 4).

Since coming onto the scene, Carbon Design Systems has focused primarily on speeding up generated software models. At DAC, it will demonstrate added resources that accelerate system performance in addition to model performance. Through what's termed Carbon On-Demand technology, Carbon's tools will begin leveraging the fact that most hardware models, especially in SoCs, are dormant most of the time. Carbon will also unveil its Model Distribution Program, which enables Carbon users to distribute the same Carbon models they're using internally to their external and internal customers.

PHYSICAL DESIGN
Planning and optimization of I/Os across the multiple domains of ICs, packages, and printed-circuit boards (PCBs) is a growing timesink, not to mention a source of increasing cost. At DAC, Sigrity will display OrbitIO Planner, a tool that provides a full physical view of all interconnect domains comprising a system, as well as the ability to explore and optimize the I/O interfaces across these domains. With shipping ensuing in the third quarter of 2007, pricing starts at $58,000 for a one-year license.

Apache Design Systems will unveil its Sentinel power- and noise-analysis tools targeted at the optimization and signoff of package and board designs. Sentinel-CPM is a chip-system power-integrity tool that produces a full-chip model of the IC's power-delivery network, containing information such as on-die decoupling capacitance and switching current profile. Sentinel-CTM is a chip-system thermal-integrity solution that provides a 3D power model that generates and ultimately provides the power density for each of the chip's surfaces to package and system thermal simulation.

Ponte integrated its YA System, a model-based technology that provides automated design-for-manufacturing (DFM) analysis and optimizes a design prior to tapeout, with Blaze's Halo lithography simulator and Cadence's Virtuoso Layout Editor. The end result is that IP and custom layout designers can view and correct DFM issues during design. By using the IP checker flow to correct potential issues, designers can both eliminate yield-limiting issues and make their IP more robust to process variability.

SoftJin will demonstrate version 3.0 of Nirmaan, a development toolkit that can be used to build post-layout and DFM applications. The company claims a tenfold improvement in performance over previous releases. Annual licenses start at $100,000. Version 3.0 will be available in June.

SoftJin will also introduce NXCompare, a multiformat layout and/or mask comparator tool that provides fast, accurate, customizable, and independent verification of post-layout operations common in DFM and fracturing. Annual licenses start at $25,000, with shipping slated for June 2007.

Claimed as the world's fastest layout viewer, Micro Magic's MAX-View will be on display at DAC. The viewer has been shown to load and display a chip design with a trillion transistors, with instantaneous redisplay at any zoom level. With the viewer's interface to Mentor Graphics' Calibre, users also can check for DRC errors. Nominally licensed for $8000/year, MAX-View is available with license fees waived until mid-June 2008.

Berkeley Design Automation will arrive at DAC with its Analog FastSPICE, RF FastSPICE, and PLL noise-analyzer tools. The company claims the tools deliver full Spice accuracy while running five to 10 times faster than any other tools for analog and RF design verification. Berkeley's Precision Circuit Analysis technology combines the accuracy, performance, and robustness needed to thoroughly verify gigahertz-speed designs in nanometer-scale silicon.

Sandwork Design will demonstrate updates to various tools in its Analysis, Verification And Debugging (AVAD) suite. SpiceCheck, a netlist-driven programmable design checker, now supports 64-bit operating systems as well as the Mentor ELDO and Cadence Spectre netlist formats.

Hierarchical 3D resistance and capacitance extraction was added to Tanner EDA's L-Edit chip-layout suite for analog/ mixed-signal design. The new tool, HiPer-PX, accurately models parasitics occurring across metal layers as well as between the metal layers and the chip substrate (Fig. 5).

HiPer-PX starts at $21,495 per seat and will be available in the fourth quarter of 2007. Existing L-Edit users can add this capability for $15,995.

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