Electronic Design

DAC Preview: Verification

Still regarding verification as the biggest timesink in your design cycle? At DAC, there’ll be many vendors looking to help you break up the bottleneck.

If formal verification is your bag, check out Real Intent in booth 706 for a preview of the two new products in the company’s EnVision family. One, called Conquest, moves beyond block-level verification using assertions to what Real Intent terms "cluster-level" verification. The tool combines a powerful formal engine with a new assertion visualization capability. Conquest makes use of standard assertion languages including PSL, SVA, and OVL.

Also new from Real Intent is Ascent, which it calls a step forward in automatic formal verification. The tool focuses on automatic design checks derived from RTL. It supports PSL and SVA constraints to find bugs in RTL code; it serves as a signoff step before RTL is checked into the design process. The tool finds a comprehensive list of sequential design bugs, including array bounds violations, full and parallel-case pragma violations, finite state-machine deadlocks, and dead code.

Novas Software (booth 3573) continues to make improvements to its debug tools. At DAC, they’ll show a new set of capabilities that streamline the process of analyzing and debugging assertion failures for users of SystemVerilog Assertions. Embodied in the latest release of the Verdi debug system, these capabilities automate the SVA debug process and give designers a more efficient means of understanding the structural and temporal relationships within the assertion constructs, as well as the relationship between the assertions and the design itself.

In addition, Novas will display an optional module for Verdi that enables users to visualize and debug complex communications protocols using transactions. The nTX module leverages SystemVerilog by allowing users to describe protocols using assertion constructs and to extract the related activity as transactions. This makes transaction-based analysis available even to designers working at the register-transfer level.

For much more on verification tools and technologies at DAC, check the July 6 issue and its full DAC preview at www.elecdesign.com, ED Online 12943.

Still regarding verification as the biggest timesink in your design cycle? At DAC, there’ll be many vendors looking to help you break up the bottleneck.

If formal verification is your bag, check out Real Intent in booth 706 for a preview of the two new products in the company’s EnVision family. One, called Conquest, moves beyond block-level verification using assertions to what Real Intent terms "cluster-level" verification. The tool combines a powerful formal engine with a new assertion visualization capability. Conquest makes use of standard assertion languages including PSL, SVA, and OVL.

Also new from Real Intent is Ascent, which it calls a step forward in automatic formal verification. The tool focuses on automatic design checks derived from RTL. It supports PSL and SVA constraints to find bugs in RTL code; it serves as a signoff step before RTL is checked into the design process. The tool finds a comprehensive list of sequential design bugs, including array bounds violations, full and parallel-case pragma violations, finite state-machine deadlocks, and dead code.

Novas Software (booth 3573) continues to make improvements to its debug tools. At DAC, they’ll show a new set of capabilities that streamline the process of analyzing and debugging assertion failures for users of SystemVerilog Assertions. Embodied in the latest release of the Verdi debug system, these capabilities automate the SVA debug process and give designers a more efficient means of understanding the structural and temporal relationships within the assertion constructs, as well as the relationship between the assertions and the design itself.

In addition, Novas will display an optional module for Verdi that enables users to visualize and debug complex communications protocols using transactions. The nTX module leverages SystemVerilog by allowing users to describe protocols using assertion constructs and to extract the related activity as transactions. This makes transaction-based analysis available even to designers working at the register-transfer level.

For much more on verification tools and technologies at DAC, check the July 6 issue and its full DAC preview at www.elecdesign.com, ED Online 12943.

TAGS: Components
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