Electronic Design

DAC Tackles Emulation, Speed, And Standards

Scheduled for June 8-12 in Anaheim, Calif., this year’s Design Automation Conference will feature a greater focus on hands-on sessions. Designers can expect to learn about solutions they can take back to their labs and put to work right away. Attendees also can expect key developments in emulation, speed, and standards.

Connecting Emulation To Testbenches
At DAC, EVE plans to showcase its ZEMI-3, a high-speed link between emulation and testbench design. ZEMI-3 moves design teams away from in-circuit emulation and offers a way to validate software in SoC designs faster, at megahertz instead of kilohertz speed, something a testbench may not be able to do.

With ZEMI-3, design teams can quickly and efficiently write transactors. These transactors are fully backward-compatible with SystemVerilog, allowing ZEMI-3 code to work in either emulation or simulation in the same way, without the need for libraries, conversions, or licenses.

Further, ZEMI-3 eases development of bus-functional models (BFMs) because of its behavioral compiler. Clocks between emulation and the testbench are automatically synchronized when needed—and only when needed. The system automatically streams data when possible, making sure the data is moved to its destination before it’s needed. ZEMI-3 is available now and starts at $80,000.

Novas Software plans to display its 2008.04 release of the Siloti Visibility Enhancement tool. This release expands Novas’ Siloti Replay technology to make the process of detecting, isolating, and fixing the source of timing problems using gate-level simulation much more efficient.

Besides offering easier integration into existing simulation flows, the Siloti Replay module now requires only minimal changes to the user’s compilation environment. It simplifies setup and configuration of timing simulation replay sessions.

Spicing Things Up
In the detail-oriented world of analog/RF design, any boost in speed is welcome. Nascentric thinks it has contributed to this with its OmegaSim GX, the world’s first hardware-accelerated Spice simulator. OmegaSim GX harnesses the raw computational power of Nvidia Graphics Processing Units (GPUs) to provide blazingly fast, transistor-level simulation with virtually no loss in accuracy.

OmegaSim GX is based on Nvidia’s Tesla hardware platform, which provides a massively parallel, multithreaded architecture. The platform is available as a 128-core PCI Express add-in card, a 256-core desk-side, or a 512-core rack-mounted system configuration. Nascentric developed OmegaSim GX using Nvidia’s CUDA C-compiler development environment. OmegaSim GX software costs $25,000 per year or $2500 per month.

Berkeley Design Automation is debuting two new capabilities for “big analog/RF” verification. One, the noise analysis option (NAO), is a comprehensive noise analysis tool. NAO is built on the company’s Analog Fast-Spice (AFS) circuit simulator, which provides true Spice-accurate results five to 10 times faster, and with five to 10 times higher capacity than traditional Spice.

The company is also introducing AFS Co-Simulation, which enables design teams to co-simulate their transistor-level netlist with Verilog simulators to further accelerate verification of complex analog/RF blocks that contain significant digital logic. It also performs full-chip mixed-signal performance simulation.

At DAC, Agilent will show update 1 of its Advanced Design System 2008 with its analysis and verification for RFICs, RF modules, and high-speed gigabit serial link designs. The major improvement is a tenfold speed bump for the suite’s Momentum planar-3D electromagnetic (EM) simulator.

Agilent will also display version 4.2 of its GoldenGate software for simulation and analysis of integrated RFIC designs. GoldenGate’s simulation algorithms are optimized for full characterization of complete transceivers. GoldenGate takes advantage of both frequency- and time-domain simulation capabilities to perform necessary analyses on today’s mixed-signal RFICs. Agilent’s GoldenGate Release 4.2 is available now, with prices starting at about $42,000.

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For those seeking compliance with the RTL Design Style Guide of the Japanese STARC consortium of ASIC foundries, Aldec will show its ALINT 2008.06 STARC Lint design-rule checker. At any time during the verification flow from design entry to synthesis, Verilog and/or VHDL designs may be run through ALINT software, which compares Verilog and/or VHDL design languages against more than 280 pre-installed STARC design-rule guidelines (a pre-installed set of STARC rules).

This brings engineers instant feedback on structural, coding, and consistency problems early in the design verification cycle. Double-clicking on reported violations cross-probes directly to the line of Verilog and/or VHDL source code that’s creating the violation. ALINT is available today, and time-based license prices begin at $7500. Engineers may download a free 30-day evaluation license at www.aldec.com.

A newly launched startup, Nusym Technology, will have a demo suite at DAC to show off its “intelligent verification” technology, which uses design insight to enable rapid verification closure while leveraging existing methodology infrastructure. Nusym’s approach isn’t to treat designs in black-box fashion, but rather to report on real verification coverage, producing precise tests for hard-to-reach design structures while eliminating redundancy.

Celebrating its 20th anniversary, Tanner EDA will demonstrate version 13 of its tool suite and preview its 13.1 release. Tanner will also preview the Linux version of Tanner Tools with support for Red Hat Enterprise Linux V4 and V5, on the x86 and x86_64 platforms.

For analog/mixed-signal IC design-rule checking and netlist extraction, Tanner EDA’s HiPer Verify has been significantly enhanced with the introduction of Calibre- and Dracula-compatible hierarchical netlist extraction capability. HiPer Verify provides default property computations for built-in devices, or user code may be written to compute custom properties from a set of pin and auxiliary layers. Look for this feature with V13.1 in the fourth quarter. At DAC, there will also be demonstrations of a 64-bit Windows version of HiPer Verify.

Standards Evolving
At DAC, the Open Core Protocol-International Partnership (OCP-IP) will make available the latest revision of the OCP standard, OCP 2.2 Rev. A, which now includes consensus profiles. The organization will also provide a glimpse into the content for OCP 3.0.

The OCP-IP will also roll out its Debug Specification and whitepaper, as well as sponsor a Debug Workshop with ECSI. The specification details an approach to a standardized OCP-bus-compliant debug interface. The solution, an optional OCP port, implements a debug interface socket that can be added to all cores and IP blocks.

The specification supports a uniform method of on-chip system analysis and access to embedded information at the core, multicore, and system levels. The debug interface socket defines several layers of extended functionality to address the diverse and increasing debug needs for software, hardware, and mixed SoC prototyping.  It’s intended to be compatible with other industry standards efforts that address debug and related on-chip issues.

Also on the OCP-IP’s plate is Part 1 of its NoC Benchmarking Specification. It details requirements and features for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Furthermore, it discusses ways to measure and benchmark reliability, fault tolerance, and testability of the on-chip communication fabric. There will be announcements at DAC regarding Part 2 of the NoC Specification.

TAGS: Components
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