Wireless Systems Design

Design-For-Test System Fits Desktop

This DFT-Focused Engineering Test System Is A Low-Cost, Laptop-Sized Option For Both SoC Designers And Product Engineers.

Wireless designers are very well acquainted with time-to-market pressures. In hopes of escaping this familiar tension, they warmly welcome anything that can reduce these pressures—especially if it also lowers product-development costs. Among the technologies that fit into this category is Teseda Corp.'s Validator 500 (V500) Design For Test (DFT)-focused engineering test system. Currently, this system is gaining popularity among system-on-a-chip (SoC) designers.

The V500 Validator is not a full-blown production tester. Instead, a low-cost, laptop-sized unit allows the design and product engineer to perform a range of critical DFT-type test functions. These functions include chip and test validation debugging, fault isolation, and engineering sample qualification.

In contrast, a full-blown Automatic Test Equipment (ATE) tester is known for providing incredible flexibility. It can generate any type of test pattern at any cycle and voltage level. Yet all too often, cost limits the use of these testers to the manufacturing floor. Although Teseda's V500 Validator engineering test system provides less flexibility than an ATE tester, it is available at a significantly cheaper price. In fact, the V500 base system is downright reasonable compared to a price tag of $2000 per pin for a low-end ATE System. The V500 Validator is priced at just under $137 per pin. Its cost makes it ideal for the engineering development environment.

In both size and functionality, the V500 is designed for benchtop or office-desktop DFT-focused engineering tests. Physically, the tester is a slim 2.7 in. (67 mm) high by 13.8 in. (350 mm) wide (see figure). It is 11.5 in. (292 mm) deep. The V500 can interface with a personal-computer (PC) workstation running any of the popular operating systems (e.g., Microsoft Windows 2000/Windows XP Pro, Linux, or Sun Solaris).

The existing V500 version includes DFT-Intelligent Software for the processing and display of stuck-at (DC) and delay (AC) scan validation. Additionally, it handles mainstream built-in self-test (BIST) methodologies like memory BIST and logic BIST as well as boundary scan (IEEE 1149.1). The V500 also boasts DFT-optimized hardware with 50-MHz data rates. Behind each pin are 32 million test vectors.

Recently, improvements were made to the existing version of the V500. These changes expand the system's basic features while adding new capabilities. Take the transition and delay (AC) scan test support, which is an optional feature. It has been expanded to provide effective test rates of 300 MHz. Another optional feature—memory and logic BIST support—now flaunts integrated clocking to 700 MHz.

In addition, the integration of Direct Drain Quiescent Current (IDDQ) support now includes the automated control of the QD-1010 Current Measurement monitor from Q-Star Test. This monitor is used for standard, delta, and current-ratio IDDQ methodologies. Like scan and built-in self testing, IDDQ is a structural test approach. It detects silicon defects without requiring any knowledge of the function of the circuit being tested.

The new version of the V500 also flaunts expanded I/O logic voltage and device-under-test (DUT) power-supply flexibility. As a result, it can handle a wider range of IC devices. Thanks to the addition of 16 clock pins, larger and more complex chips also can be handled. The total supported system pin count is now up to 348.

To ease the process-integration burdens of its users, the V500's API allows test flows to be customized. Plus, the V500 integrates easily into most design flows through the support of common tool suites. For example, the DFT-Intelligent Software—part of the V500 package—directly imports and displays device-specific scan information. It gets this information from Standard Test Interface Language (STIL) IEEE 1450-1999 ATPG files. These files can be generated by Synopsys' TetraMax, Mentor Graphics' FastScan, and others. The information that is imported from ATPG files includes device signals, scan structures, timing, and test data. Support for compression tools, like Mentor's TestKompress and Synopsys' SoCBIST DBIST/XDBIST, also is included.

On the display side, users can view vector-table-character and waveform diagrams. Among the other viewable items are filtered signal lists and structural scan chains and cells.

The V500 Validator is available now. The base system price is $60,000.

Teseda Corp.
315 SW Fifth Ave., Suite 1100, Portland, OR 97204-1753; (503) 223-3315; FAX: (503) 223-3316, www.teseda.com.

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