Electronic Design

DSP Advances Tackle More Complex Audio Algorithms

As digital audio algorithms get more complicated, DSP architectures are evolving to keep pace.

Digital audio basically started with the introduction of the CD music format. Since then, digital music and audio recording and playback have overtaken analog audio storage and playback as the dominant technology. Advances in DSP performance and continually decreasing DSP chip prices have both played enormous roles in making this possible.

But the audio algorithms that encode and decode the digitized music are constantly improving. These enhancements, along with new audio formats—ranging from the basic 2× CD sampling to Real Audio, Windows Media Audio, MP3, THX, and others—continually challenge the DSP engines. They must handle ever more complex algorithms that deliver better quality audio, reduce the number of bits per audio file, and offer additional features, like reverb and 3D spatialization.

Processing basic CD audio requires 10 to 20 MIPS of DSP horsepower, while MP3 music algorithms need between 20 and 30 MIPS. Some newer algorithms, which reduce the number of bits necessary to store and reproduce the music, take more complex computations and more compute power—typically 50 to 100 MIPS.

Achieving 20 MIPS or so on a dedicated DSP chip or an embedded DSP core, or even on a CPU with some DSP assist logic, is relatively easy for chips fabricated with mainstream 0.25-µm and smaller design rules. The DSP engine can handle all of the algorithms for standard CD and MP3 playback. The remaining functions a player typically needs include button control, housekeeping, motor control, and display management. Such functions were initially implemented in a more control-oriented device, like a microprocessor or microcontroller.

Some DSP chips—including the TMS320C25x and the new TMS320-DA250 series from Texas Instruments (TI), the DSP56F807 and DSP56852 from Motorola, and the ADSP219x family from Analog Devices—feature control-oriented instructions, enabling a single-chip solution. These chips can tackle the motor control functions in a CD player, or other tasks.

Yet the era of standalone DSP chips for the low-end systems is fading as system-on-a-chip (SoC) integration lets designers combine the DSP and control processor, and often the digital-to-analog conversion, mixed-signal output circuitry. New, improved DSP or CPU cores give designers a wide range of performances from which to choose. Some embedded CPU cores, like those by Advanced RISC Machines (ARM), ARC, Hitachi/STMicroelectronics, Tensilica, and others, offer DSP enhancements like a hardware multiplier-accumulator (MAC) or a DSP coprocessor to help speed the computations.

Over the last few years, the number of suppliers of standalone DSP chips has been reduced to just three main contenders: Analog Devices, Motorola, and TI. Intel Corp. and Analog Devices have co-developed a new 16-bit architecture called Blackfin, while Motorola and Agere Systems have teamed up to develop the STARcore architecture.

Earlier this year, Infineon decided to halt work on its proprietary Carmel DSP technology and join Motorola and Agere as a third partner on STARcore. Infineon will add the intellectual property (IP) developed for Carmel to the pool of resources for future STARcore development. Hitachi Semiconductor and STMicroelectronics have pooled efforts to extend the Hitachi-created SH processor family into the DSP space. The SH3DSP and SH4DSP processors have resulted from this collaboration.

Several companies offer DSP engines as licensable blocks of IP. As previously mentioned, ARM, ARC, and Tensilica have embeddable CPUs with DSP enhancements (the ARM9D, ARCtangent, and Vectra, respectively).

Other offerings include a family of cores from the DSP Group (the Oak, Pine, Teak, Teaklite, and the just released Cedar) and an extensible core dubbed Saturn from Adelante. Several companies feature a number of building-block cores, like the BOPS MAN array, Improv Systems' Jazz core, the LSI Logic LSI402ZX and 403LP (based on the ZSP architecture that LSI acquired by purchasing ZSP Corp.), and the 3DSP Corp. SP-3, -5, and -20 cores. (To learn more about configurable DSP engines, read "Reconfigurable Architectures Chart A New Course For DSPs," Electronic Design, Aug. 5, p. 46, or view the archives at www.electronicdesign.com.)

In addition to generic DSP chips, several companies have developed application-targeted chips for the multimedia market. Cirrus Logic crafted the CS494xx series of single-chip audio processors for mid- to high-end equipment in the home entertainment industry, the CS493xx series for the mid-range, and the CS492xx series for entry-level entertainment equipment. For the portable entertainment market, the company just recently introduced a low-power chip targeted at low-cost multiformat CD players (standard CD audio, MP3 audio, and Microsoft WMA audio), the CS7410.

The most recent addition to the entertainment-centric family, the CS49400 fits AC-3 and APP audio applications. Its custom Harvard architecture DSP engine has dual 32-bit MACs and 72-bit accumulators that can perform over 500 Moperations/s. (The large accumulators help minimize distortion due to round-off errors that could occur if smaller word lengths were used.) Software downloads configure the audio processor and allow it to support all standard encoder formats. A pulse-code-modulated (PCM) processor executes DSP algorithms for tone control, parametric and graphic equalization, bass management, delay insertion, volume control, and much more.

Taking aim at the low-cost end of the entertainment market, the Cirrus CS7410 is an integrated audio processor for portable multiformat CD players (Fig. 1). Designed to operate at very low power levels, the chip and the remaining control and interface circuits would allow a player to run for up to 12 hours or so on a single set of batteries. Based on a proprietary 16-bit DSP engine and a 32-bit RISC core, the chip includes 256 kbytes of ROM, 80 kbytes of RAM, and an 18-bit delta-sigma digital-to-analog converter.

TI's TMS320DA250 provides a low-power, high-performance solution for portable MP3 players and other devices. Much more than just a DSP chip, it can deliver up to 800 MIPS of DSP compute throughput along with many system support functions—a USB 1.1 port, 128 kwords of RAM, three multichannel serial ports, two multimedia-card (MMC), secure digital (SD) serial ports, two memory stick serial ports, a 32-kword by 16-bit maskable ROM with secure bootloader, and a 64-bit unique secure device ID.

Competing with TI and Cirrus is SigmaTel, which offers an MP3/WMA player on a chip, the STMP3410. The D-Major audio decoder is targeted at all-solid-state players and would enable a player to operate for up to 35 hours on a single AA battery. The chip supports digital rights management and just about all the digital storage media types—SmartMedia, MMC, Secure Digital, Compact Flash—as well as SDRAM, CD, and IDE devices.

Going after other consumer entertainment areas, TI has developed the TAS3103 digital audio processor. Powered by a 48-bit fixed-function DSP core, this chip can support input and output 32-bit data streams. When clocked at 135 MHz, it delivers a throughput of 540 MIPS. Software provides algorithm support for various 3D/surroundsound effects and much more.

Another single-chip solution, Analog Devices' SoundMAX, is a digital-audio subsystem-on-a-chip for use on PC motherboards. SoundMAX comes in either two- or six-channel configurations and features audio I/O jack sharing, array microphone support, software configurable speaker equalization, and the SPX sound production extensions. (SPX uses sound behaviors that eliminate the repetitive nature of sound effects processing, generating sounds that constantly change and evolve.)

Capable of much more than simply audio processing, the Cedar, Blackfin, and STARcore embeddable DSP engines target applications from audio to complex video processing. Interestingly, all three share some similar traits. Each is scalable and lets designers pick from several configurations that can include one, two, four, or eight 16-bit MACs. Their scalability allows designers to select the best tradeoff between DSP resources and chip area (cost).

Cedar can offer word-size scaling for the native data-word size—16 bits for consumer audio and other applications, 24 bits for professional-grade audio and other higher-resolution requirements, and 32 bits for the highest precision and widest dynamic range. The basic core in the CedarDSP operates at 450 MHz and uses a nine-stage pipeline to ensure all of the MACs can be kept busy.

A 16-bit word, four-MAC version, the Cedar1640 architecture comprises two MAC clusters plus a data address and arithmetic unit, a program control unit, and a memory subsystem (Fig. 2). Each MAC cluster contains two multipliers, an ALU, a bank of 16 accumulators, and a bit-manipulation unit. The device is scalable by replicating this cluster up to four times.

The Blackfin processor is based around a data and arithmetic unit that includes two 16-bit MACs, two 40-bit arithmetic units, four 8-bit video ALUs, and a single 40-bit barrel shifter. Each MAC can perform a 16- by 16-bit multiply on four independent data operands every cycle. Initial implementations of the dual-MAC version operate at 300 MHz to perform 600 million MACs/s.

Also initially targeted to run at 300 MHz, the STARcore SC140 DSP core can deliver a throughput of 1500 MMACs thanks to a quad ALU architecture. The basic building block used by Motorola and Agere to implement DSP chips, the core can deliver top-notch performance. For instance, Motorola recently released the MSC8102, a 16-bit DSP chip based on the SC140. The MSC8102 packs four SC140 cores, pushing up the throughput to 6000 MMACs (Fig. 3). That makes this chip the highest-throughput 16-bit DSP released to date.

To achieve that throughput, every ALU in the SC140 core contains both an arithmetic unit and a MAC, 224 kbytes of local SRAM, 16 kbytes of real-time instruction cache, a four-entry write buffer, a program interrupt controller, and an enhanced filter coprocessor that supports matrix multiplication and other complex operations. The MSC8102 packs four of these cores, 476 kbytes of level 2 shared SRAM, and a high-performance 32/64-bit system bus that can run at 100 MHz.

Although this chip could make short work of multimedia audio, its mainstream application would really be voice-channel processing in 3G wireless basestations and other multichannel telecommunications applications. For instance, one chip can accomplish all of the processing for eight DSL channels, or more than 60 universal channels (voice/fax/modem), over 80 compressed channels with over 64-ms carrier-class echo cancellation, and up to 600 noncompressed G.711 voice channels.

Of course, many other powerful DSP chips are available from Analog De-vices, Motorola, TI, and other companies. Although processing multimedia files would be short work for them, their main applications in the audio space would mostly be in telecommunications applications where a chip might serve as a filter bank or handle hundreds of voice channels in a voice-over-Internet-protocol (VoIP) system.

Need More Information?
Adelante Technologies
[email protected]

Advanced RISC
Machines Ltd.

(408) 579-2200

Agere Systems Inc.
(610) 712-4323

Analog Devices Inc.
(800) 262-5643

ARC International plc
(408) 437-3400

(650) 254-2800

Cirrus Logic Inc..
(510) 623-8300

DSP Group Inc.
(408) 986-4423

Hitachi Semiconductor
(408) 433-1990

Improv Systems Inc.
(978) 927-0555

Infineon Technologies Corp.
(408) 501-6000

Intel Corp.
(408) 765-8080

LSI Logic Inc.
(866) 574-5741

Motorola Inc.
(512) 895-2000

SigmaTel Inc.
(512) 381-3700

StarCore Technology
Center/StarCore LLC

(770) 937-4504

(602) 485-6100

Tensilica Inc.
(408) 986-8000

Texas Instruments Inc.
(972) 644-5580

3DSP Corp.
(949) 435-0600

For DSP benchmarks
and market data:
Berkeley Design
Technology Inc.

(510) 665-1600

Forward Concepts Co.
(480) 968-3759

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.