A NODE-HIGHLIGHTING FUNCTION is among the new features in L-Edit v11.1, Tanner EDA's analog/mixed-signal design platform. This function lets users display all of the geometry connected to a node in a circuit layout, regardless of hierarchy. Users can quickly identify and debug differences between layout and schematic netlists. Node highlighting improves design productivity significantly during layout-versus-schematic (LVS) checking. For example, when LVS indicates an open circuit between two nodes, the nodes can be highlighted to determine where a missed connection might be. It also helps locate accidental short circuits. L-Edit v11.1 is available now with pricing starting at $5995 per seat. Visit www.tanner.com for more information.
TRANSISTOR-LEVEL DEBUGGING is made easier in the Cadence Virtuoso schematic-editor environment by a product from Concept Engineering. An option to Concept's SpiceVision Pro, the product automatically generates schematic fragments—critical paths or sections of a circuit—and exports them into the Cadence environment. Once that's accomplished, designers can use the fragments to perform transistor-level debugging and optimization. Surrounding circuit structures don't affect the fragments during debugging, so simulation takes less time. The schematic fragment export capability is available as an option to SpiceVision Pro. Contact Concept Engineering for pricing. For details, visit www.concept.de.