With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis (STA), among other improvements, to an already ASIC-like FPGA design flow.
The SmartTime STA environments support the growing complexity of today's FPGAs. In its timing analysis view, it graphically displays all of the design's clock domains and lets users add constraints and perform analysis (see the figure). Clock domains easily can be added or subtracted. The timing-analysis view is tightly integrated to a constraints editor. Many changes can be made in the timing-analysis view, and the constraints view is automatically updated.
In the constraints-editor view, timing requirements and exceptions can be edited with easy to use "visual dialogs," which guide users toward capturing constraints quickly and correctly. These views are tightly integrated to the timing-analysis view as well, allowing users to quickly see the impact of changes.
For Actel's recently introduced ProASIC 3 family of logic devices, the Libero environment now performs automatic clock assignment of up to 18 clocks. It automatically determines the clock networks and large-fanout networks, placing the nets with appropriate drivers.
Also, v.6.2 of the Libero environment offers free access to Mentor's ModelSim AE (Actel Edition) simulator in the Libero Gold edition. The Libero v6.2 integrated design environment comes in a Platinum edition for Unix ($4995) and Windows ($2495) as well as in a free Gold edition for Windows. The Platinum edition handles unlimited device sizes and contains physical synthesis capabilities from Magma Design Automation.