Keep The Cost Of In-Car Displays In Check

According to market researcher DisplaySearch, approximately 22 million LCDs will be used in by 2008 (the total was near 12 million in 2004). The interfaces between the graphic controller as a video source and the timing controller, which distribute this information to the individual pixels of the LCD display, will constitute a very important system function (Fig. 1). The frequencies, as well as the data and clock rates, occurring with the transmission paths of remote, increasingly larger and higher-resolution LCD modules can’t be controlled as analogue video signals. Nor can they be covered by conventional digital automotive communication standards (CAN, MOST, or most recently by FlexRay). USB and "Firewire" IEEE1394, in their electronic and optical versions, are mainly used for in-car driver information and entertainment systems. Because of the enormous protocol layer overhead, however, they don’t represent a cost-efficient system solution for a pure, transparent function for video raw data transfer to a display.

Since the end of the 90s, the differentiated signalling standard LVDS (low-voltage differential signalling) has established itself in its serialiser/deserialiser (SerDes) version in this field. Multiple serialiser-deserialiser designs have been developed to further refine this approach for specific requirements in the automotive sector. Minimising the pair of wires in transmission cables is an important development trend in this case. That’s because significant system costs aren’t included in the actual transmission components, but rather in the cable paths and connectors. Here, the aim is always, of course, to use cost-efficient twisted-pair cable constructions.

Low-Voltage Differential Signalling (LVDS)

Only the electric driver output and receiver input characteristics are defined with the LVDS signalling standard (TIA/EIA-644-A-2001). This is a purely physical-layer technology, which leaves the definition or usage of upper protocols open and flexible. A LVDS sender includes a constant power source that creates the appropriate digital level change from logic high to logic low at the receiver. It does so by switching current direction (3.5mA nominal) in a pair of lines of the transmission medium. A simple passive termination at the receiver complements the current loop and forms the line termination. Figure 2 summarises the design and the specific benefits of LVDS signalling technology.

Due to the small voltage swing from 250 to 450mV, very high data rates of up to 1Gbit/s and more are possible. Both the static current consumption and the dynamic current portion are very low. In addition, the power driver with its constant impedance can keep power consumption relatively constant over a wide frequency range. Power spikes, common in the switching of TTL or CMOS ("push/pull") outputs, are also minimised through controlled impedance. Finally, termination-resistance power is very low due to the low current (only 1mW).

For signal integrity and EMV behaviour, critical system benefits result from the low signalling level and the differentiated transmission design. Though the electromagnetic fields of the respective conductors of a pair have the same value, they change 180° in phase. The field intensities are proportionally coupled to the distance of the conductors. To achieve optimal cancellation of the fields, this distance should be kept as small as possible in the same way as it’s ensured, for example, in twisted pair cable connections. Just by minimising conductor distances, field intensity portions can, for instance, be reduced to 15dB. The wide ±1V common-mode range of the receiver manages common-mode interference signals. The relatively moderate edge steepness of the signal transition’s dV/dt, in the range of less than 1V/ns, is also favourable with respect to EMV emissions.

Serialiser/deserialiser designs

The number of possible serialiser/deserializer (SerDes) designs is wide and varied. A couple of them are particularly interesting for the transparent function of video transfer to an LCD: serialization on a number of data channels with a parallel clock channel ("Channel Link" chips sets); and serialization only on a differential channel with an embedded clock signal ("Bus LVDS SerDes" chip sets).

The channel link design, with its 21-bit-wide parallel bus, is optimally adapted to the number of colour (18 bits at 6-bit colour depth) and control bits (three signals: "vertical sync," "horizontal sync," and "data enable") of common TFT-LCDs. Directly coupling the phase-locked loops (PLLs), which time-multiplex/demultiplex the serialisers and deserialisers, over a parallel clock channel eliminates the need for a complex and expensive clock-data-recovery (CDR) mechanism in the receiver.

The parallel TTL signals of the graphics controller are time-multiplexed by the channel link sender in a 7:1 ratio and converted to LVDS level. The channel-link receiver then deserialises the data and forwards them to the parallel TTL output for further processing of the flat-panel display’s timing controller (TCON) of the flat-panel display. In this way, the total throughput is distributed to multiple channels, limiting the data rate per channel. The transmission path length is limited by tolerance with respect to time skew between the channels at the deserialiser. The data channels and the clock channel must not run too far apart in time to ensure correct demultiplexing. This design allows for up to 5m twisted-pair cable, as a standard value, to be achieved (depending on data rate, system design margins, etc.).

The bus LVDS SerDes design, on the other hand, reduces the number of lines for a differential transmission standard to merely two wires. Not just a single data stream is serialised, though. The clock, in the form of start/stop bits, is also embedded: Skew is no problem here, and the maximum controllable cable path is defined in most cases by jitter tolerance of the deserialiser.

The required lengths of the cable paths, of course, depend on the position of the host and receiver systems. For example, cable lengths of 8m and more may be required between a DVD player in the central console and a display screen on the rear side of the headrests. These are absolutely feasible with the LVDS SerDes design. This is also made possible by, among other things, allowing a higher driver current than the standard driver current to be injected into the lines with the so-called "Bus LVDS."

Contrary to "LVDS," Bus LVDS isn’t an official standard. Implementation is specific for the respective chips and chip sets. A momentary disadvantage with this design is that even with chipsets available in full production, the parallel bus width is still limited to 18 bits. It may be necessary to do without least-significant bits, or TFT-LCDs must be selected because they can also function without DE (Data Enable) signal.

System design tips and tricks

Even if the LVDS technology meets all requirements with regard to emission and susceptibility, all relevant standards should be considered and appropriate design precautions taken to comply with EMV provisions. These apply to the board layout (e.g., the proper positioning of analogue and digital logic to keep current loops of TTL-return currents small) and adequate filtering of power supplies. Also, board layers must have sufficient reference/image planes, and critical signal paths carrying periodic signals with high slew rates must be implemented in strip line configurations.

Proper selection and connection of connectors is another important criterion. For EMV optimisation, it’s absolutely necessary to connect the cable and connector shieldings carefully to avoid faults. Not only for the fast LVDS signals, but other signal paths should be carried out correctly to avoid crosstalk and skew, as well as to minimise current loops for return currents.

Important parameters for LVDS-connection signal integrity are the data rate, signal attenuation and inter-symbol interference (depending on cable quality), as well as jitter. It’s of great benefit that, with respect to well-controlled switching thresholds and a higher tolerance toward jitter and skew, reliable data transfer can be achieved with cost-efficient twisted-pair cables. Very advanced reception characteristics of the respective deserialiser devices make this possible.

As a transparent and slim interface, the LVDS signalling standard provides a very favourable system solution for LCD applications in cars. In fact, LVDS already implements robust and fast interfaces on a physical layer in display systems for cockpits, central consoles, or the backseat area. Its different serialiser/deserialiser chipset versions constitute broadband, rugged, and cost-efficient interfaces for a wide range of LCD based displays in cars. Last but not least, its low total system costs, minimal power consumption, and low EMV are very convincing.

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