Memory Matters

In many cases FPGAs are built using SRAM technology that means devices lose their memory after power-down. Joerg Kaleita discusses one possible answer.

In addition to industrial applications, image processing is beginning to play an increasing role in automotive engineering. In this market CMOS image sensors are used for applications like capturing the sitting position of the driver and co-driver for optimum airbag triggering. The common denominator of all these applications is the need for digital circuitry for control and data processing functions.

The main function of the control logic is taking signals from CMOS sensors and generating control signals, such as vertical and horizontal clock pulses for displays, as well as chip enables. These benefit from properties such as constant turnaround times and usually require very high speeds if higher-speed sensors are used. In most cases, rather than requiring very large numbers of logic gates, wide structures are needed for operations such as reading address signals.

To implement such control tasks, various different approaches, or architectures of programmable logic devices, are available to developers:

  • product-term-based architectures (CPLDs)
  • gate-array-based architectures (FPGAs).

The advantage of product-term based architectures is the availability of very wide structures due to the AND/OR matrix at the inputs of logic blocks. Because of the central routing matrix around which the logic blocks are placed, control signals can be generated with almost identical propagation times. This is ideal for control tasks.

Such devices are non-volatile due to EECMOS technology which is usually used. The disadvantage of this architecture is the smaller number of available logic elements as compared to FPGAs.

Gate-array architectures have no central switch matrix. Instead, they provide correspondingly more logic blocks which are interconnected by vertical and horizontal routing lines. This is not ideal for control tasks for which constant propagation times are often needed.

In most cases, FPGAs are built using SRAM technology resulting in the devices losing their memory after power-down. It is, however, possible to implement memory into the device. It is also possible to use the built-in PLLs in today's commercial FPGAs for control signal generation.

A blend of both technologies would be ideal; a non-volatile, product-term-based architecture also providing memory, PLLs and diverse system IOs. These are the characteristics of Lattice's XPLD architecture. Following SPLDs and CPLDs, XPLDs are the third generation of product-term-based architectures. The ispXP technology provides a built-in EECMOS memory and SRAM memory.

The EECMOS memory preserves the configuration when turned off. The configuration is copied to the volatile SRAM memory within 200µs after power-on. This means the devices can be used when signals need to be generated immediately after power-on, such as chip-enable signals (instant on). A threshold circuit ensures reliable function even in the presence of strong voltage fluctuations. Figure 2 illustrates the XPLD architecture.

XPLDs are the third generation of product-term-based logic devices. As is typical with CPLDs, separate logic blocks are interconnected via a central switch matrix in such a way as to ensure constant propagation times, meaning that, in principle, propagation time is not affected by where a signal comes in and where it goes out.

Logic blocks, as already known from CPLDs, are called multi-function blocks (MFBs) in XPLDs, as they can be operated in different modes – as 'normal' logic with a corresponding AND/OR matrix in front of the registers, or as FIFO, dual-port RAM or CAM. With the MFB operated in logic mode, 32 macrocells are available.

In this case, extremely wide structures allow routing of up to 160 product terms (OR operation) with 136 signals each to both polarities. Through dual-XOR technology it is possible to simultaneously implement in one macrocell both a registered function and a combination function. Additional carry-chain technologies within the respective MFBs allow fast arithmetic functions.

As the AND/OR matrix is implemented using SRAM cells, the MFB can also be configured as memory with each MFB providing 16kBits. The individual MFBs allow cascading.

Although, in principle, a separate clock network is available to each register due to the routing matrix, two analogue PLLs exist in each XPLD. This makes sense, as it is possible, amongst other things, to use these PLLs for clock multiplication or for optimum adjustment of signals from outside the device through phase shifting.

The system IOs support all current standards such as LVTTL, LVCMOS, SSTL and HSTL, but also differential and therefore less error-prone standards, such as LVDS and LVPECL. As another special feature, using LVTTL or LVCMOS3.3, the IOs still are 5V-tolerant, despite the use of most modern manufacturing technology. In addition, the IOs are hot-socketing capable and therefore very robust, even in 'rough' environments. Voltage supply is from one source – either 3.3V, 2.5V or 1.8V – with no specific switch-on sequence being required.

The application was implemented using an XPLD as shown in Figure 3. This delivers the required signals to the CMOS sensor. Using the PLLs, the clock rate provided from the control module was multiplied allowing the generation of the required signals in very fine alignment to the timing pattern with the signals being significantly smaller than the clock period. The control logic itself can be adjusted by the control module over the I2C bus.

The image signals coming from the CMOS sensor are temporarily stored by lines in a dual-port RAM. Subsequent data pre-processing determines the focal point from the previous line, only transmitting to the control module its position in the line plus ten signal values adjacent to the focal point (brightest value). In this way, the data rate to be transmitted was reduced and the CPU on the control module relieved. In this application, data was captured using the light-section method for 3D identification, only requiring the focal point in the line.

Communication with the control module is effected using the LVDS differential transmission standard with transmission-side interferences affecting both lines (P and N) and being eliminated at the receiver. Due to the small current requirement and the single-supply concept of the XPLD, voltage could even be supplied using a twisted-pair line.

For this application, the Lattice XPLD was a good solution. The major challenge consisted in the very limited space available for the camera module. Housed in an fpBGA package, the XPLD is the only device on the PCB apart from the CMOS sensor and a number of discrete components.

See associated figure 1

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