Electronic Design

Parallel Backplanes Face Competition From Serial Solutions

Everyone knows that the world is analog in nature, yet we insist on dealing with analog signals by digital means. Analog sensor outputs are quickly converted to digital form to improve noise immunity and make use of the benefits of digital signal processing, a conversion that carries costs with it. Single-wire analog signals are replaced with wide, inherently parallel digital data, with the width of the data driven by the dynamic range of the system and by the required signal-to-noise ratio.

Parallel data transmission is the customary solution for short-distance communication, particularly for moderate clock rates. Transmission distances are limited by the allowable skew between signal lines. Higher clock rates reduce the timing budget that can be allocated to path differences, media variability, and transceiver output variations. When transmission distance and clock rate aren't an issue, parallel communication still suffers from drawbacks of signal count, power demands, connector size, pin count, and EMC issues associated with single-ended signaling used in parallel architectures.

Serial data transmission solves many of these shortcomings. While not new, it's seeing greater acceptance as its capabilities increase. Telecommunications, data communications, video display, and imaging are among the end applications where it's widely used.

A vast array of serialization devices is available to choose from. Many use differential signaling to improve performance in the presence of noise and reduce radiated emissions when balanced signaling is used. Noise immunity allows for lower voltage transitions, which leads to higher signaling rates, an obvious necessity for serialized data. Reductions in pin counts, power, copper, and cable size result in cost savings, while also enabling solutions where mechanical constraints are important.

Fixed- and programmable-width devices are now available offering serialization ratios up to 40:1 and supporting wider inputs via multiple data lines. A wide spectrum of parallel-input clock rates are also supported. LVDS devices alone support serialization of data from below 10 MHz to above 100 MHz. Data signaling at multigigabit rates is readily available. Numerous solutions employ a separate clock signal that travels with the serialized data. Others embed the clock to reduce interconnect requirements and alleviate skew issues of parallel data transmission.

Different topologies are supported with serialization devices as well. The most common is for simplex, point-to-point communication links. Other devices support multidrop architectures where a single source distributes data to multiple links. Full-duplex solutions also are offered for simultaneous, bidirectional communications with support up to multigigabit rates.

The throughput benefits of wide parallel buses will yield to the efficiencies of serialization as the achievable device signaling rates grow. Multipoint serializers will replace parallel multipoint architectures. Parallel backplanes will also see increased competition from point-to-point serialized solutions. Cost-sensitive designs will migrate to serialized data to utilize the possible economic savings. Designs with mechanical challenges will embrace the flexibility of serialized solutions with more efficient cabling needs. We can also expect greater integration of serialization functionality inside programmable devices and EMC issues associated with the usual single-ended signaling used in parallel architectures.

The same benefits that drive discrete solutions apply to integrated solutions. Designers will decide to transmit serially, followed by a choice between integrated or discrete solutions. The latter will have to evolve and incorporate greater functionality to remain competitive.

TAGS: Components
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