Electronic Design

Ring In The New

A potpourri of announcements at DAC today spanned the gamut of EDA tools and technologies, ranging from ESL to the OASIS file format for mask-data preparation. In between were some interesting new analysis tools and a tester for first-silicon validation.

On the ESL side, ARM’s RealView System Generator is aimed squarely at software developers for ARM-based platforms, enabling them to generate instruction-accurate virtual prototypes that are not only reusable, but fast enough to interact with in real time. The tool gives both hardware and software engineers the ability to create and modify their own system models. The speed of the generated virtual prototypes is said to be comparable with currently available mobile devices. With the prototypes, users can then test application software months before hardware is available.

RealView System Generator addresses the growing problem of mobile systems with varied functionality, i.e. phones that play MP3 files or game systems that can display video. In such systems, software issues must be ironed out long before hardware prototypes are ready to ensure that the user experience is gratifying.

System Generator operates through a drag-and-drop GUI that enables users to quickly create and deploy complete virtual system prototypes. A library of ARM processors and key peripherals is ready to go. Also, software developers can use the tool to build their own IP models for addition to the library.

Apache Design Solutions has added to its lineup of power analysis tools by incorporating thermal analysis. Sahara-PTE helps designers more fully untangle the leakage-current problem at 90 nm and below by accounting for the temperature variations of a chip design. More heat means more leakage, which in turn means more heat. There’s also the thermal effect on clock skew and electromigration to consider. All of these effects are accounted for by Sahara-PTE, thanks to its high-capacity simulation kernel.

In combination with Apache’s RedHawk power-integrity tool and PsiWinder timing/noise integrity tool, Sahara-PTE provides a full answer to the power-thermal-electrical loop (hence the PTE name). Pricing for Sahara-PTE starts at $160,000 for annual licenses.

Berkeley Design Automation came to DAC last year to launch its PLL noise analyzer. This year, they’ve extended their core capabilities to launch two tools in the Spice category. Analog FastSpice and RF FastSpice both deliver full Spice accuracy at 5X to 10X performance without requiring block-level tuning. Analog FastSpice uses a multi-rate transient engine to deliver robust DC convergence. Target applications include any transient simulations that require full-Spice accuracy, such as full 802.11 a/b/g transceivers, sigma-delta ADCs, DTV tuner automatic gain control with bandgap and bias, high-speed I/O, and post-layout multi-GHz PLLs.

RF FastSpice adds unified time/frequency, harmonic balance, and stochastic non-linear engines to Analog FastSpice’s functionality. The result is robust periodic convergence and VCO phase noise proven within 1db relative silicon accuracy. Target applications for RF FastSPICE include any complex RF blocks (for example, multi-frequency and highly non-linear blocks) that cannot converge in traditional RF simulators, or have greater than one hour runtime. Examples include: 65-nm PLLs, 90-nm LC-tank and ring oscillator VCOs (including bandgap and bias), 130-nm low-noise amplifiers (LNAs) plus mixer circuits, power amplifiers, and crystal oscillators.

A conversation with Kathy Werner, president of the VSI Alliance, revealed that an update of VSIA’s hard-IP tagging specification is forthcoming in the near future. Along with that will be a tool that’s been donated to VSIA for reading, writing, and maintaining IP tags.

OneSpin Solutions, an Infineon spinoff that’s exhibiting at DAC for the first time this year, is showing its 360 Module Verifier (360MV) formal verification tool (see ED Online 12545). OneSpin is crowing about an application of the tool at Infineon on a protocol processor IP block. The block, consisting of about 30,000 lines of VHDL code, was exhaustively verified by the 360MV tool against its original functional specification with 4 engineer-months of effort. That represented a total verification effort of some 40% less than was required to verify an earlier version of the same IP block.

On the silicon-validation front, Advantest Technology Solutions is at DAC talking up the first fruits of its CertiMAX event-based test technology. The CertiMAX model 105 test system enables users to directly use .vcd simulation data to drive silicon test. Further, the tester’s compact architecture fits into a small tabletop rack system in a 6U PXI chassis. Events on each pin of the device-under-test (DUT) are treated independently as opposed to being cyclized according to time sets. The tester’s architecture eliminates the rate generator, pattern memory, waveform memory, and timing memory found in traditional cycle-based testers. Instead, they’re replaced with event memory and event-generator capabilities.

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