Electronic Design: What's driving the
trends in IP reuse today?
Gary Delp: There's a strong financial need for reuse rather than recycling of IP. That distinction between reuse and recycling is important. Recycling is where you take someone else's work as your base. You understand it in detail and use key parts. But you don't reuse components.
But in ideal reuse, the IP that you're reusing encapsulates the expertise of its designer(s). That requires consistency of packaging. The cost of producing a high-quality IP deliverable highlights the importance of protecting the value of that IP, and not just the IP itself, as it's being transferred.
I know that when I receive an update for a block of IP, I'll often spend almost as much time processing the update as I did processing the original version. So consistency of packaging is a strong need in the industry, and it's on the roadmaps of both VSIA and the SPIRIT Consortium.
ED: What about the content of the deliverables?
GD: That issue is being addressed by SPIRIT with IP-XACT (see the figure). And the quality is being addressed very effectively by the VSIA's Quality IP (QIP) Metric. At LSI, internally and with our suppliers, we use the QIP Metric for crisp communication of expectations and evaluation of deliverables.
If someone is new on a project and they need to reuse a piece of IP, they may not know all the right questions to ask from the start. The QIP Metric acts as an expert tutorial on the right questions and concerns.
VSIA has completed a full rewrite of the QIP Metrics' vendor qualification, the soft-IP deliverable portion, and the hard-IP portion, both for the components and the integration. During the summer, we'll launch a QIP Metric extension for embedded software.
ED: What's the status of the VSIA's IP-tagging initiative?
GD: IP tags, or watermarks, provide the ability to track the provenance of a piece of IP. Where did it come from? And who needs to get paid for it when it ends up in chips? As a systems integrator, I find IP tagging critically important. It helps you ensure the IP that you verified is the same version that you're taping out.
ED: Are tool providers building in the capability
to not only read these tags, but to make efficient
use of them?
GD: The VSIA's Encryption Working Group, or Open IP Working Group, is putting together a structure that not only lets you intermix clear-text blocks and encrypted blocks inside of IP deliverables, the group is also adding write-management tagging.
Write-management tags can be provided to each particular tool or qualified tool vendor that say "I trust your tool to decrypt this file. I trust it to display the file and to not write out anything in the log file about this file so that it's being obscured." Or, the tags might say, "You're permitted, in this use, to write obfuscated or clear text." Integrating that capability in a standard form for IEEE-standard VHDL, Verilog, or SystemVerilog design files can go a long way toward preparing protected deliverables for FPGA usage.
As a result, the value of the IP can be protected, in turn enabling IP providers to supply deliverables to a much larger group. It also could lower IP costs to users because the development costs are amortized over a larger base. The whole ecosystem benefits.
ED: When will a write-management standard be
GD: The write-management structure is about to be reviewed, after which we'll need preparation time for the standard. We'll also work with Accellera's working groups for the IEEE-1076 and -1800 standards, with the possibility that those standards would be modified. The industry is being really helpful on this.
ED: Wouldn't this proposal be valuable in the verification flow?
GD: Yes, the verification flow is a key aspect. But it also means you can distribute configurable IP, or IP that will be optimized in the synthesis flow. The availability of certain high-level information would enable synthesis tools to perform much more effective optimizations, but that information is in itself valuable IP. So you now have the ability to communicate that valuable structural information to the tool without revealing it. I think the incremental benefit of getting more flexible, higher-quality synthesis results will help drive this into the flow.
Also, SPIRIT has accepted Denali Software's donation of SystemRDL, which is a way of describing registers (see "IPMetadata Standard Gains Automatic Register Mapping,"). The working group will ensure that the data being described in SystemRDL can also be captured in IP-XACT and that there's a definitive translation. By having the RDL Alliance and SPIRIT work together, we'll have a converged data model. I'm really pleased with the success that this will drive going forward.