System-On-Chip Targets Digital Set-Top Boxes And TV Sets

The requirements of digital satellite, cable or terrestrial receivers are satisfied by adding only memory, an appropriate front end, and interface components to designs based on a new system-on-a-chip. The µPD61030 set-top box device includes all of the core circuitry necessary to decode an MPEG-2 stream and present it for display. It also generates the graphics associated with electronic program guides and the other interactive applications that digital television is expected to provide.The chip integrates: a code-efficient, 64-bit, 100-MIPS VR4110 processor with MIPS16 support; a MPEG-2 transport stream demultiplexer; a MPEG A/V decoder; and a graphics engine. Peripheral support functions include: smart-card interfaces, IEEE 1284 support, a parallel port, I²C interfaces, and UARTS. The prime function of the device is to receive a demodulated MPEG-2 transport stream, which contains compressed program material together with other information, and decode it for display on a television screen. Its architecture differs from that of existing Integrated Receiver Decoders by virtue of its ability to display overlayed graphics material and on-screen display data directly from system memory. The unified CPU and graphics memory allows the device to render graphics images and display them directly without having to copy them to a separate display memory. System memory is also used by the transport stream processor, which allows graphics objects that are being downloaded by the transport stream to be displayed immediately from the same memory with minimal processing.