Logic analyzers have long been the tool of choice for debugging complex timing and finding elusive functional problems. For parallel bus architectures, they offer time-correlated analysis of hundreds or thousands of simultaneous channels to uncover complex system timing or functional problems. With state acquisitions up to 1.5 Gbits/s, logic analyzers continue to provide the sample speeds necessary for most synchronous parallel buses. They also correlate with other tools like oscilloscopes to provide digital data time-correlated with analog data for additional insight into the system under test.
With multigigabit serial and parallel interfaces such as InfiniBand, Serial ATA, Hyper Transport, XAUI, and PCI Express, logic analyzers continue to provide historical measurements, as well as offer protocol packet visualization. This data display is time-correlated to other parallel system activity, such as memory buses or processor buses. For most multigigabit serial solutions, the logic analyzer uses a high-speed front-end analysis probe to sample data and recover the clock. Data is then transferred to the logic analyzer at a slower rate for acquisition and analysis.
Protocol analyzers aren't typically available when a new high-performance serial bus like PCI Express is introduced. Much of the physical-layer and system functional validation for PCI Express, for the first hardware prototypes, has been done exclusively by logic analysis for lane widths up to X16 before protocol analyzers were available.
The logic analyzer offers a complementary solution to an oscilloscope or protocol analyzer for design engineers testing physical-layer core logic or system functional interaction. It allows protocol analysis on a serial bus to be time-correlated with other system activity to trace data through the system or correlate multiple transactions from multiple serial buses.
Logic-analysis displays have also evolved with the hardware-acquisition capabilities from the familiar waveform and state listings. Now they include protocol displays of the highest-level protocol information down to the raw bit level. Protocol decode tools also have trigger macros that automatically set up the sequence levels in the logic-analysis modules by simply entering trigger values of the protocol fields.