A highly integrated cell and packet traffic management engine, the PaceMaker 2.4 is said to provide state-of-the-art quality of service (QoS) that supports the full OC-48c data rate. The first in a family of products to address packet and cell processing problems found in the core routers and multi-service switches at the heart of theInternet, the device reportedly includes the industry's first OC-48c ATM AAL5 segmentation and reassembly (SAR) engine that supports up to 256K independent sessions. According to the company, the PaceMaker 2.4 is also the world's first silicon implementation of the Earliest Deadline First (EDF) scheduling algorithm, which has been theoretically proven to be the optimal mechanism for traffic management. The chip was designed and developed by Orologic, Inc., which was recently acquired by Vitesse Semiconductor Corp. It is packaged in a single 756-pin ABGA device and is priced at $1,095 in sample quantities. Production quantities will be available in September.
Company: VITESSE SEMICONDUCTOR CORP.
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