The new Gx 3000 series builds on the same architecture but cuts power consumption and reduces the Ethernet port count to deliver a chip that is ideal for the cloud. Each 1.5 GHz 64-bit VLIW core draws less than 0.5W cutting power by 80%. The chips still incorporate a wire-speed packet engine delivering 40 Gbit/s throughput. Likewise, the MiCA engines include 20 Gbit/s crypto support and they can compress/decompress packets at 10 Gbits/s.
The 36-core chip (Fig. 1) is available now and the 100-core chip will be available later this year.
|# of 64-bit VLIW cores||36||64||100|
|Frequency ( up to 1.5 GHz)||1-1.5||1-1.5||1-1.5|
|Cache size (MB)||12||20||32|
|Physical address bits||39||40||40|
|64-bit DDR3 controllers with ECC||2||4||4|
|1 Gigabit ports||4||8||8|
|10 Gigabit ports||1||2||2|
|PCIe 2.0 controllers||1x 8-lanes
|Sampling dates||Q2 11||Q1 12||Q4 11|
Tilera's iMesh network actually implements a parallel set of interconnects. One network handles cache coherency for Tilera's DDC (Dynamic Distributed Cache) while others handle memory and communication operations. The mesh also provides TileDirect coherent I/O support. Each core has a mesh switch node associated with it.
The VLIW cores support virtualization and have DSP and SIMD instructions that can be very handy for embedded applications. The architecture supports hardware parititioning so groups of cores can provide isolated computing islands. The system also provides Zero-Overhead Linux (ZOL) support. Essentially ZOL is a tickless Linux environment that is very handy for efficient packet processing.
Tilera's Eclipse-based open source IDE, Multicore Development Environment (MDE) provides a standard set of compilers and debuggers. Tilera also provides advanced debugging and profiling tools for the Gx 3000 Series.
The chips support a range of standard platforms like the Red Hat Enterprise Linux compatible CentOS, programming frameworks like Intel's Thread Building Blocks (see Multiple Threads Make Chunk Change), Erlang and OpenMP (see Software Development For Embedded Multi-Core Systems).