Electronic Design

45-nm Via-Programmable ASICs Add High-Speed I/O Transceivers To Feature Mix

ASIC design starts have plummeted in recent years, and there are many good reasons why. Designs at ultra-deep-submicron process nodes are awfully expensive and getting more so daily as mask costs rise, software content proliferates, and verification takes longer. Meanwhile, the steady rise of application-specific standard products (ASSPs) has also contributed heavily to the ASIC’s marketshare slide.

Thus, many designers have turned to alternative vehicles for implementation, including FPGAs and via-programmable (or structured) ASICs. The latter have seen a resurgence in the past few years as via-programmable ASICs have not only kept pace with FPGAs in terms of features, they’ve also outpaced them in terms of density and speed.

The latest generation of eASIC’s via-programmable ASICs, dubbed Nextreme-2, is fabricated on a 45-nm low-power process at Chartered Semiconductor. That fact alone makes them attractive, though the chips also carry up to 20M gates of logic and up to 30 Mbits of true dual-port memory (Fig. 1).

A few other attributes should give custom designers pause to look at the Nextreme-2 family. Since the devices are via-programmable, no mask charges are involved in using them, even for very small quantities. In fact, there’s no minimum order at all for these devices. You don’t even have to pay for a single entire wafer’s worth. Turnaround time is just six weeks from tapeout to first silicon.

In this latest 45-nm iteration, the family adds up to 56 multi-gigabit I/O transceivers, each capable of operating at 6.5 Gbits/s for an aggregate bandwidth of 364 Gbits/s. The inclusion of the multi-gigabit I/Os opens the way for via-programmable ASICs to compete with FPGAs and standard-cell ASICs for highperformance networking applications such as switches, routers, traffic management, metro transmission, and mobile backhaul.

In DSP applications, the devices offer performance of up to 2.4 TeraMACs. (This rating assumes 100% of the largest Nextreme-2 device working at 500 MHz with a 16-by-16 multiplier paired with a 32-bit accumulator.) According to Narinder Lall, director of product marketing at eASIC, this represents a significant performance advantage when compared to FPGAs.

“When DSPs are constructed using logic cells in FPGAs, it uses a lot of silicon real estate. For every transistor that can be used, three are used for routing. We don’t have that problem because we don’t have that switch matrix, which adds long delays and long paths to connect logic cells,” said Lall. “The limiting factor with FPGAs in a DSP system is the switch fabric.”

The Nextreme-2 devices also offer power-consumption advantages. Triple-oxide transistors are used where their speed, low-power characteristics, and density are most advantageous, primarily around the I/O transceivers. Because the devices are fabricated on a low-power 45-nm process, they offer inherently low leakage. Furthermore, selectable core voltages of 1, 1.1, and 1.2 V give users the option of achieving low power or higher performance.

Other power-saving measures include single-via power programming, which enables complete shutdown of unused eCells and memory. Columnbased clock gating can be employed to control dynamic power consumption. In addition, with this generation of the product, dynamic power control is much more granular. Users can switch off clocks to groups of flip-flops as small as 16.

In the Nextreme-2 ASIC architecture, the via layer is used to configure lookup tables. This means that there are no SRAM cells in the lookup tables, which further reduces power consumption. According to Lall, this results in a 50% reduction in static power compared to the 90-nm version and a reduction of 50% to 70% in dynamic power.

The design and manufacturing flow for the 45-nm devices begins with the user’s RTL. The company provides a free suite of front-end design tools for phase-locked loop (PLL) configuration, memory instantiation, I/O assignment, and generation of the user’s constraint files. There is also a tool for design-rule checking. At the back end, eASIC provides a free router (Fig. 2).

Users must purchase an OEM version of Magma Design Automation’s Blast Create synthesis tool. This version is usable only in the eASIC design flow and costs about 10% of the cost of the full version of the tool.

On the manufacturing side, it’s worthy to note that production can begin before the design is completed (Fig. 2, again). Once a GDSII file has been delivered to eASIC for the via4 layer, eASIC handles lithography and processes the ground and power layers. Working devices are shipped within six weeks.

Recently, eASIC has begun working with early-access customers for the Nextreme-2 and Nextreme-2T (with multigigabit I/O transceivers) families of via-programmable ASICs. The devices will become widely available during the fourth quarter of 2008. Speific pricing for these products is not yet available.

DAVID MALINIAK

EASIC
www.eASIC.com

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