Electronic Design

Advanced Processors Dominate MPU Forum

Next-generation CPUs from top microprocessor vendors will be the stars of next month's Microprocessor Forum in San Jose, Calif., hosted by MicroDesign Resources. The discussions surrounding these leading-edge chips should give system developers a glimpse of what's to come in performance and integration.

Sun Microsystems CTO and vice president Greg Papadopoulos will open the forum on October 14 with a keynote that will examine the challenges of achieving high throughputs. Fred Weber, CTO and vice president of the Computational Products Group at Advanced Micro Devices, will provide a perspective on the history and future of computer instruction-set architectures in his keynote on October 15.

The first group of presentations on October 14 will detail new CPUs for PCs and servers. Sun Microsystems will take the wraps off its next-generation 64-bit UltraSPARC IV processor architecture, designed to power the next generation of servers. IBM Corp. will show off its next-generation Power5 processor.

The remaining papers in the opening session will detail processors for desktop systems. Fujitsu will unveil its latest version of the SPARC64 VI instruction-set architecture. VIA-Centaur Technology will describe two x86-compatible processors that incorporate some novel features. Another PC-compatible CPU, Transmeta's T8000 Efficeon processor, will debut as well.

The second session will highlight a number of CPUs that deliver high computational throughputs. A low-power floating-point embedded processor for scientific computing and DSP applications is on tap from ClearSpeed Technology Ltd. MathStar's field-programmable object array can process data at 1 GHz for signal and network processing. A new member of the StarCore DSP family will show how Motorola expects to bridge the gap between general-purpose computing and signal-processing applications. And, Philips will reveal a superpipelined architecture for a new member of its Trimedia processor family.

Two massively parallel computational engines will round out the session. The first, from PicoChip Designs Ltd., targets communications applications. The other, from Silicon Hive, uses a reconfigurable ultra-long-instruction-word core to deliver flexibility.

Additional high-speed CPUs will be revealed on the second day of the forum. The morning session will focus on embedded processors. Presentations from ARM will examine deeply embedded processors. Also on the docket will be a multithreaded RISC/DSP architecture from Imagination Technologies and the new 24K family of 32-bit cores from MIPS.

Low-power processors will take center stage in the final main session. ARC International will show off its new ARCtangent A600 processor core, while ARM will reappear with a processor for mobile applications that has enhanced security features. Designers from Renesas Technology Corp. and SuperH Inc. will reveal the SH-X, a 4500-MIPS/W two-way superscalar CPU core. To close out the session, Motorola will offer a next-generation processor architecture targeting converging computing and communications applications.

In addition to the processor presentations, researchers from the University of Texas at Austin will provide an overview of their TRIPS (tera-op reliable intelligently adaptive processing system) processor project (see "Supercomputer On A Chip Promises Teraoperations," p. 25).

For further information, go to www.mdronline.com/mpf/conf.html.

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