Electronic Design

ASIC Industry Hits Critical Economic Stage

The application-specific integrated circuit (ASIC) market faces several economic and technological factors that call into question its ability to survive and prosper. Even after recovering from the dramatic decline in market revenues that started at the end of 2000, this market must come to terms with many issues that confront it in the near term.

On the economic front, the rising cost of mask sets and very large nonrecurring engineering (NRE) charges may force smaller customers and startup companies to rethink their product strategies and possibly delay their designs from entering the production stage. This may also push these companies toward using field-programmable gate arrays (FPGAs) as a production technology. In addition, the well-identified flow of ideas and innovative solutions derived from smaller companies in the semiconductor industry can be stymied by these high startup costs.

Another disturbing trend today is the longer design cycle for high-end ASICs and system-on-a-chip (SoC) solutions. Designers find themselves in the unenviable position of seeing product life cycles and windows of market opportunity shrink while design-cycle times increase. Electronic-design-automation (EDA) tool vendors are addressing the design-cycle problem with better and more comprehensive tools that provide more control to designers over their work. However, the increase in potential gate counts due to smaller process geometries offsets any boost in designer productivity that comes from using better tools.

A counter-trend is the greater use and reuse of semiconductor intellectual property (SIP) blocks. The result is that designers can pick the SIP best suited for their design and capitalize on the expertise of others. The SIP industry has its own set of issues, such as the interoperability between SIP blocks in a design, quality control, and the portability between silicon vendors.

Semico believes that an important technology trend in the ASIC market is the introduction of die-area efficient memory cells from companies like MoSys. The ability to implant numerous CPU or DSP cores onto SoC silicon is rather moot without also attaching enough memory to ensure that processor performance is kept at optimum levels. Embedded memory solutions such as the Mosys 1T-Q (one transistor-quad density) SRAM cells let reasonable amounts of memory be tied to the processors embedded on the chip.

Even though ASIC vendors seem to be under attack from all sides, they will survive the current assault. A customer simply can't acquire a silicon solution with the lowest possible cost and still have the highest possible performance without pursuing an ASIC design. What has changed is that the volumes needed to justify an ASIC have grown to where low- and now medium-volume applications are almost forced to use FPGAs or application-specific standard product (ASSP) solutions.

TAGS: Digital ICs
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