In a move to 0.13-µm design rules, Texas Instruments is offering two versions of an enhanced CMOS ASIC process. One is optimized for high performance, and the other targets applications with low standby power.
Thanks to its 95-nm drawn-gate lengths, the SR40 option doubles the speed of previous company offerings. Circuits implemented on the process achieve basic gate delays as short at 25 ps, allowing core logic speeds over 600 MHz. Library elements are available in up 11 drive strengths to let the design tools optimize performance and timing closure.
To obtain the high performance, the company employs a low-k dielectric between the six layers of second-generation dual-damascene copper metallization. A seventh layer is optional. The combination achieves a 46% reduction in interconnect delay and reduces on-chip signal interference. Circuits implemented with the SR40 process can operate from supplies as low as 1.2 V.
The GS40 option, however, uses slightly longer drawn gates—110 nm—to achieve power levels as low as 0.011 µW/MHz/gate. The process uses five layers of dual-damascene copper metallization, with an optional sixth layer, to reduce on-chip delays. The circuits can run from 1.1- to 1.5-V supplies, and the I/O lines can operate at 1.8, 2.5, or 3.3 V.
Designers can make use of a wide variety of library cells and large blocks of intellectual property, such as DSP cores and serializers/deserializers. SRAM compilers let the SR40 process pack up to 32 Mbits of SRAM on a chip, along with other IP. Also, designers can pack up to 450 kbits/mm2 on the GS40. The SR40 option supports up to 1000 pins on wirebond packages and up to 2500 contacts on flip-chip and other ball-based packages.
Both of the processes are now available for new designs. NRE fees and ASIC pricing depend on complexity and packaging.
Texas Instruments Inc., 13500 N. Central Expwy., P.O. Box 650311, Dallas, TX 75265; (800) 336-5236; www.ti.com/sc/docs/asic/modules/index.htm.