Be savvy when moving to full digital power-supply control

With the advent of cost-effective and powerful processors in the marketplace, digital solutions have entered a number of what were previously purely analog systems. For example, high-quality electric motors today are almost exclusively digitally controlled, using microcontrollers or DSPs. Motor speed and torque can be variably and precisely set due to the secondary control of current and voltage.

This isn't yet the case in related applications, such as current or voltage supply in power supplies, in which the control of amplitudes and frequencies of current and voltage must be performed. Analog control systems still dominate these areas, though the trend here also is moving toward digital control.

Full digital control of switching-mode power supplies offers a number of major advantages. The ability to control the power-supply operation through software often makes it possible for a single hardware implementation to meet the precise needs of a wide range of different products. Furthermore, designers can easily upgrade power supplies simply by installing new firmware. Digital power-supply control also offers the potential to provide much more powerful control functions, including adaptive control routines that adjust power-supply output based on operating or environmental conditions.

The advent of digitally controlled power supplies, though, raises some significant performance issues. Analog controllers are based on continuous time, so performance usually isn't a limiting factor. Digital controllers, on the other hand, must address time quantization effects. Such controllers are driven by a system clock that generates granular time steps. The steps depend on the system clock frequency and the switching frequency. The resolution (in bits) of a digital pulsewidth- modulation (PWM) controller is proportional to the system clock speed and is inversely proportional to the switching frequency, as indicated by:

Re solution = LOG2 (TPWM / TSYSTEMCLK)

A new generation of digital signal controllers (DSCs) addresses these challenges, making it practical to develop full digital power supplies for a much more demanding range of applications. These controllers typically offer a modern 32-bit DSP core with a 100- or 150-MHz clock frequency; a 16-channel, 12-bit analog-to-digital converter (ADC); flexible logic for the generation of PWM signals; and numerous serial and parallel interfaces. Such features enable the design of full digital control systems that provide analog-like PWM granularity while only requiring 30- to 100-MHz system clock rates.

Table 1 summarizes the resolution of various combinations of system clock and PWM frequencies. The table also includes the number of instructions available for control in each case. It shows that with higher PWM frequencies, the resolution can rise to unacceptable levels. The effect is accentuated by the move to lower voltages, which reduces the amount of the PWM period that can be utilized. As a result, the step change in time is no longer a percentage adjustment of the full period, but instead must be considered as a percentage of the proportion of the full PWM period that's actually used.

The PWM resolution must be at least two times better than ADC measurement accuracy, which in turn needs to be two times better than the set-point accuracy required by the power supply. So if the output voltage needs to be maintained at ±2 %, then the ADC resolution has to be at least ±1% , and the PWM must control output voltage to at least ±0.5 %. Clearly, the PWM resolution values shown for higher PWM frequencies are unable to handle all but the least demanding output-voltage requirements.

The latest generation of DSCs overcomes this problem by offering a high-resolution mode. Texas Instruments' TMS320F280x, for instance, extends the 16-bit compare register to 24 bits, which dramatically increases PWM resolution at a given clock frequency. Table 2 compares the resolution of this DSC in conventional and high-resolution modes, showing that accuracy is increased by a factor of 50 across the PWM frequency spectrum.

Modern DSCs also address another source of output-voltage error—the ripple voltage. A conventional PWM generates a ripple of approximately 30 to 35 mV, or approximately 3.5% of output voltage (see the Figure). This creates serious problems in satisfying the demanding power requirements of CPUs, FPGAs, and memory systems that often require 1% accuracy. Enabling the high-resolution capability reduces ripple to approximately 5 to 6 mV, or approximately 0.6% of the output voltage ripple.

PWM resolution and ripple problems can exacerbate each other. If the PWM resolution isn't sufficient, the output voltage will continually be out of tolerance, triggering frequent adjustments in a phenomenon known as limit cycling. A low-resolution PWM signal tends to bounce between distinct values because the PWM generator can't accurately position the PWM pulse edge as commanded by the digital controller. In contrast, modern DSCs can position the pulse width to an accuracy of 150 ps, providing a clean and singlefalling edge transition. This substantially reduces the uncertainty in the output voltage (Table 2).

A single DSC can easily handle multiple power converters. The number of simple buck converters can be determined in relation to the control or PWM frequency. The standard buck converter algorithm can be executed in assembly in 26 clock cycles by using 32-bit interim and result values. This corresponds to a control time of 260 ns at 100 MHz, or 171.6 ns at 150 MHz. An additional 41 cycles are required to store and rewrite the context and to service the internal ADC. Adding these cycles makes it possible to calculate the number of buck converters that can be controlled at a given PWM frequency.

TAGS: Digital ICs
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