The Si5364 SONET/SDH port card clock IC is said to exceed the jitter requirements of both OC-192 and STM-64. Providing Stratum 2/3E-compliant protection switching, the chip produces four clock outputs with less than 0.25 ps (typical rms) of jitter in OC-192 applications. The company's proprietary DSPLL technology is claimed to be responsible for the low jitter figure, while SiLECT technology allows the integration of hitless switching with clock synthesis circuitry. The chip phase locks to one of three reference clock inputs and generates four outputs that can be individually configured in the 622-, 255- or 19-MHz range. For applications that use forward error correction (FEC), selectable 15/14 or 14/15 scaling of the clock multiplication ratios between the input and output clocks is provided. Other features of the clock IC include an integrated voltage regulator and operation from a single 3.3V or 2.5V supply. Available in an 11 mm x 11 mm BGA, samples are available now with production scheduled for third quarter of this year.