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Co-Verification Environment Spans Both CPU & DSP Cores

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Using the firm's Coherent Memory Server technology, version 3.0 of the Seamless Co-Verification Environment (CVE) can now embrace both CPU and DSP shared-memory architectures found in a growing number of telecommunication designs. Enhancements to the tools target the unique characteristics of DSP cores, such as multiple data buses and long word operations.Other new capabilities include a 3X performance improvement, new algorithms for high-speed RTOS simulation, and the Seamless Plug-In Interface. The latter exposes internal structures to facilitate integration of third-party applications, including virtual instruments and memory analysis tools. Seamless CVE provides a platform for early evaluation of embedded software against the embedded core ASIC design. Embedded code on a virtual prototype is debugged, and both hardware and software are more likely to be correct on first pass.

TAGS: Digital ICs
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