Two core products, the 10 Gigabit Physical Coding Sublayer (PCS) and the Media Access Controller (MAC), are intended for use in Xilinx’s Virtex-II and Virtex-II Pro field programmable gate arrays (FPGAs). The PCS core implements a 64- to 66-bit gear box, provides a generic 16-bit microprocessor interface, a variety of performance monitoring counters, and programmable value of control codes and corresponding 7-bit code mappings. The MAC core supports full duplex operation, PAUSE frame-based full duplex flow control, both LAN and OC-192c data-rate WAN PHYs, WAN PHY using open loop (IPG stretching) rate control, Link Fault Signaling (LFS), and VLAN tag frames.The cores, together with previously announced cores, make up a complete 10 Gigabit Ethernet LAN and WAN IP core package for programmable system designs. Applications at the edge of a metropolitan area network (MAN) include multi-service switches, add-drop multiplexers, digital cross-connects, traffic aggregators, and test equipment. Core-based FPGA designs are a way to lower time-to-market pressures. The cores are compliant with IEEE P802_3ae sub-layer specifications and IEEE 802.3 frame specifications. Both the PCS and MAC cores are available immediately. For more details, contact: PAXONET COMMUNICATIONS INC., Santa Clara, CA. (510) 770-2277, ext. 119. XILINX INC., Santa Clara, CA. (408) 879-5381.
Company: PAXONET COMMUNICATIONS INC.
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