Anyone who uses a cell phone, digital camera, or television set-top box can see why the semiconductor industry is under pressure to find new solutions for today's design problems. Today's consumer devices demand new levels of flexibility from processors and technologies to adapt to numerous and fast-changing standards, even while placing restrictions on die size, power consumption, and throughput. As a result, the adoption of a configurable DSP processor architecture, which can be "right sized" for a specific application, is emerging as a critical step to meeting today's market requirements.
A configurable DSP system provides a way to extend the device's instruction set and computational and memory resources, as well as a tool suite that supports "custom" DSP processor implementation. In the fully realized configurable DSP system, the application developer isn't constrained to existing fixed DSP architectures. Rather, it can drive the hardware in the direction necessary to best support the application. Appropriate compilation and analysis tools let the designer quickly optimize the DSP for the specific application, eliminating unneeded hardware elements to reduce size and cost. Because the design system is application driven, support for new standards and upgrades is fast and incremental.
If you have to pare down the performance drivers in a DSP system to the essentials, you would select parallel execution, memory access, and application-specific accelerators. For the flexibility and control required in such a system, very long instruction word (VLIW) has become the processor of choice. This is because VLIW provides parallel execution of operations with the degree of parallelism determined at compile time.
As for data memory access, traditional DSP processors generally have a dual-data (X, Y) memory architecture. Configurable VLIW processors exceed this capability by allowing the number of memory interface units (concurrent memory operations) to be configured. With appropriate tool support, this can be accomplished without additional logic design, and the processor's performance can be significantly increased through a simple configuration change.
Designers working with configurable processors can achieve major gains by adding custom logic into the data path. However, the VLIW approach offers other significant configuration options. A key capability is the option of adding parallel datapath elements, like ALUs and MACs. In many signal-processing applications, this capability alone can yield a significant performance increase. For these applications, more performance can be gained by simply modifying the processor configuration to include an additional parallel MAC unit.
Aside from performance gains, this type of modification to the processor's architecture configuration has the benefit of not requiring logic design for a new operation. The modified (customized) processor simply includes another copy of an existing unit. For still further performance gains, the included units can be custom elements designed by the user. While this brings a degree of complexity, the payoff can be considerable. Also, with the right tools, the complexity is manageable.
The home market for broadcast video has been a tantalizing plum for the past several years. There's a clearly identified mass market for in-home, high-quality individualized entertainment and information content. Yet, the design of set-top boxes for cable and satellite feeds has remained relatively stagnant. Several well financed and highly visible projects to provide unified access points for home entertainment have been costly failures due to their inability to meet target price points, lack of needed features, or missing critical-time deadlines. The rapid movement toward increasing complex and demanding video, audio, and data standards has stymied conventional set-top box designs as MPEG2 moves to MPEG4, and now to the emerging ITU H26L video compression standard.
This application exemplifies today's design problem where the ability to track and implement multiple emerging standards is the key to success. The programmable, configurable DSP system with sophisticated compiler and unified design/implementation tool support provides the answer.
A successful design for configurable processors must, from its inception, involve the concept of application optimization, not add-on tools to support a nifty hardware design. This means the coordination of many elements: compilation tools, analysis tools, platform design, functional library development, partner integration for implementation and system components, and coherent user interfaces to make the system workable.
At the core, the VLIW compiler must perform code generation, optimization, and processor allocation, while being tightly coupled to the platform configuration analysis tools. This coordinated design system empowers the user to make intelligent choices and easily modify them as requirements evolve. Next-generation designs can build on existing work without having to start from scratch.