Electronic Design
Consumer Product Designs Drive New Thinking In Selecting Power Regulators

Consumer Product Designs Drive New Thinking In Selecting Power Regulators

The emergence of energy-efficiency standards and the continued evolution of processing and feature sets to support new products that consumers and enterprises use in everyday life have changed the methodologies employed for addressing dc power conversion, management, and distribution.

Many consumer product designs traditionally haven’t been as concerned with standby-power dissipation, dynamic load currents, or smaller form factors as, for instance, the wireless handset industry. The advent of these challenges in addressing power-management solutions is driving new thinking in the selection of power regulators for powering ASICs, DSP chips, systems-on-a-chip (SOCs) with a core, memory, and I/O supplies in these products.

Designers will be looking to leverage the benefits of new high-frequency regulator solutions like Fairchild Semiconductor’s FAN5354 (3 MHz) buck regulators with techniques to provide high efficiency over wide load currents (1 mA to 3 A), significantly reduce load transient response, and offer very small form factor solutions due to reduced component size and count.

Power designers working with these applications historically have focused more on low-cost regulators ICs with less than 1-MHz switching frequencies where external components are used to ensure soft-start, stability, filtering, and optimization of the load transient response. Until recently, these end markets weren’t primarily concerned with standby power drain and board space. Also, the dynamic electrical performance wasn’t critical to meeting system power budgets. In fact, many applications employed inefficient linear regulators up to 3 to 5 A as thermal/heat management mainly limited the power drain.

From an application perspective, the advanced consumer and industrial products that are most in need of advanced dc-dc switching regulators have several common challenges to solve:

Power consumption (dynamic and standby) standards: Total standby power regulations in Europe and North America are driving an average of less than 1 W average. This effectively requires power designers to find solutions that not only have high efficiency (typically greater than 90%) at full load, but also in load-power states when processing chips, display drivers, memory, and I/Os have to be powered in idle states (to ensure fast response to various features/user requirements) but are not active.

High-performance video, networking, displays, communications: With the advanced feature sets offered in products today, some systems blocks that draw the largest load currents are operating between 1 and 5 V dc. This includes advanced densely integrated SoC ICs, processor cores for video, displays, digital signal processing, dynamic memory access devices, and high-performance communications interfaces like high-speed USB, HDMI, and a host of new wireless standards, including Wi-Fi, Long-Term Evolution (LTE), and WiMAX. These cores are based on the latest high-density 60/45-nm processes, which require very low operating voltages (as low as 0.8 V dc) but with higher average/peak load currents (1 to 5 A) and very dynamic current consumption. For example, a load can shift from 0 to 3 A in as short as 1 µs.

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Smaller/thinner consumer product form factors: The board space and thickness profiles of higher-performance consumer products are challenging system power-design teams to find solutions that have the smallest component count and yet utilize smaller components to achieve the same performance. The higher switching frequency topologies lend themselves to reducing inductor size, but proper filtering and output capacitance depends on the architecture employed.

Consider the requirements for a performance DVR/set-top box device. The figure shows the typical power budget requirements for the 5-V dc supply rail from an offline converter subsystem.

So in addressing the type of power requirements suggested in the example of the figure, the FAN5354 can address all three key power rail requirements with an output voltage that’s adjustable from 0.8 V to 90% of VIN (VIN max of 5.5 V). The device also can deliver 3-A continuous output current at over 85% and maintain above 80% efficiency with load currents down as low as 2 mA.

This light-load efficiency is obtained as a result of the implementation of automatic transition from pulse-width modulation (PWM) control at higher load currents (typically greater than 600 mA) to pulse-frequency modulation (PFM) modes for lighter-load conditions with a typical quiescent current of 270 µA.

The device MODE pin can be controlled to force the device to stay in PWM operation. Or, it can be synchronized to an externally provided PWM signal on the MODE pin. In addressing concerns about audible noise, the minimum PFM frequency is limited to 26 kHz to keep spectrum in PFM mode out of the audible frequency range. The architecture controls the frequency in PWM mode to 3 MHz ±10%.

The other key challenge that power design methodology must consider is meeting total VOUT accuracy and error budget for the regulated supply.

A typical standard total error budget is 5% of target VOUT overall operating conditions. This total error budget is a summation of four key components:

• dc output voltage over temperature: For most regulators, this is trimmed to 1.5% max over operating temperature conditions.

• Line/load regulation: Most commercially available regulators have less than 0.5% for line/load regulation.

• Ripple voltage: VRIPPLE is generally related to the switching frequency and parasitics of passive components. The FAN5353 architecture yields performance that is independent of the output capacitor equivalent series resistance (ESR), allowing for the use of ceramic output capacitors. When driving light loads, the FAN5354 operates in discontinuous current (DCM) single-pulse PFM mode, which produces low output ripple compared with other PFM architectures. The result of this architecture is minimal impact on ripple to the overall error budget. Using, for example, a 5-V VIN, 1.2-V output with 3-A load, the device will have a typical ripple voltage of 15 mV or 1.2%.

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• Transient response: Since most regulators are trimmed or optimized for these parameters, the only remaining variable in meeting total error budget is load-step transient response. This is where the FAN5354 architecture surpasses conventional solutions. This performance is obtained with unusually small output capacitance (2 x 10-µF 0805-case ceramic capacitors) as well, allowing power designs to meet the specifications without requiring the addition of significant bulk capacitance (and cost) to improve transient response. From the product datasheet, the load transient response can be estimated. For a large load transient step of 1.5 A, the FAN5354 produces only 30 mV of total VOUT error before the regulator tracks out the transient. This represents 2.5% of error and allows for VOUT accuracy to be achieved at a low VOUT in the 1- to 1.8-V range.

So summarizing the total error budget analysis (see the table) for our example, the impact the load transient response of the FAN5354 implementation has on meeting a total 5% error budget window with some margin (about 15%) versus the limitations of conventional solutions in missing the window is significant, especially at low output voltages.

Outside of these critical performance metrics, more attention is being paid to board space. The architectural approach of the FAN5354 3-MHz solution allows for the user to meet these key specifications while using only two low-cost ceramic output capacitors with smaller capacitance values then conventionally used. This, along with the significantly smaller inductor value (470 nH) compared with solutions based on legacy 300-kHz to 1-MHz switching solutions that use inductors in the range of 10 to 33 µH, helps to create component layouts that can fit on board areas of less than 65mm2.

Chris Winkler is the marketing director of Fairchild Semiconductor.

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