True systems on silicon are now a reality thanks to advances made in process technology. This includes chips containing millions of gates, megabits of memory, and mixed-signal circuitry at designers' fingertips. But designing and fabricating such complex chips challenges designers at almost every turn.
The large number of gates presents the first challenge. Creating the system from basic gates and flip-flops is too time consuming, so large blocks of intellectual property must be used. Combining those IP blocks, however, also is a challenge because many of them weren't designed to work with each other. To make it easier to combine blocks, such as processor cores, DSP engines, memory, high-speed I/O ports, and so forth, design tools must provide ways to encapsulate the IP. By encapsulating each block, the tool can provide a common interface so that the different blocks can talk to each other and be tested once integrated into the chip.
Today, designers can purchase or license a wide array of IP from both the ASIC suppliers and independent sources. An expanding range of choices includes popular CPU cores, DSP engines, MPEG blocks, multigigabit serial I/O interfaces, mixed-signal blocks (analog-to-digital and digital-to-analog converters, comparators, and phase-locked loops), and of course memory blocks. The downward scaling of design ups the performance of most of these functions. But new problems emerge as the features and power-supply voltage scale downward. This becomes most apparent with blocks of static RAM. Standby subthreshold leakage current in their six-transistor memory cells actually rises as the operating voltage drops. For multimegabit blocks of RAM, this current can be considerable and unacceptable if the circuit is targeting portable, battery-powered applications.
One possible solution is to shift from the 6-T memory cell to a SRAM work-alike based on a 1-T DRAM-like memory core. The 1-T SRAM cells offered by Mosys provide such an alternative. Although it requires a slow refresh, a 1-T memory array actually consumes less power and has less leakage current than megabit and larger blocks of SRAM. By using this scheme, designers can economically integrate large blocks of RAM onto the ASIC, eliminating external memory chips and their associated buses.
Design features continue their downward scaling from mainstream 0.18-µm design rules in use today, to 0.13 µm, which should have widespread availability in 2003. The next level is 0.09 µm, which a few companies are putting into limited production in 2003 but won't be widely available until 2004. As the design rules shrink, however, the manufacturing costs explode. A mask set for multimegagate chips fabricated with 0.13-µm and smaller design rules might approach $1 million. But it's not only the mask cost that goes up. Nonrecurring engineering costs are higher, as will be the test costs. Those cost increases may start to limit which chips can actually get fabricated.
One alternative resurrected from the mid-1980s is the use of design platforms. Available from several companies, these platforms are partially premanufactured chips that contain a collection of resources—blocks of gates and memory, dedicated high-performance I/O, and even embedded processor cores. By offering these partially premanufactured chips, mask costs come down by more than 50% because just the last three or four metal interconnection layers must be defined. But some designs might be restrained by the limited resources prefabricated on-chip.
LSI Logic offers one possible solution with its recently unveiled RapidChip platform. In this approach, designers can define the resources on the starting silicon, thus crafting a platform that would suit their needs perfectly. The platform would be unique to their company, and designers could amortize the cost of creating the platform across multiple designs.
>INCREASED USE OF PRE-INTEGRATED "PLATFORM" chip solutions will deliver faster turnaround and lower manufacturing costs by providing a premanufactured solution that only requires three to five metal masks to customize.
>BLOCKS OF INTELLECTUAL PROPERTYwill get more complex and bring with them the challenges of integrating and testing very complex functions. Soft IP will be the biggest challenge since performance will depend on layout. But some companies are resorting to hard IP (functions with predetermined layouts) to ensure the performance of speed-critical functions.
>CONTINUED REDUCTION IN DESIGN RULE DIMENSIONS, from today's 0.13 to 0.09 µm by late 2003 and to still smaller feature sizes in 2004, will allow ASIC designs to incorporate tens of millions of gates.
>ASICS WILL INCLUDE LARGER AMOUNTS of on-chip static memory to help reduce system complexity and improve system performance. New technologies such as the 1T-SRAM developed by Mosys promise to considerably increase the amount of memory that can be integrated on the chip. The latest implementation, known as 1T-Q, offers a fourfold improvement in memory density versus memory blocks based on six-transistor storage cells.
>HIGHER-SPEED MULTIGIGABIT SERIAL I/O INTERFACES will be incorporated on ASICs to deal with the increasing demand for higher data bandwidth. Such interfaces will also help keep the exploding pin count for bus interfaces under control since one serial link might typically replace eight bus signal lines.
>USE OF EMBEDDED DRAM BLOCKS will start to increase as manufacturers overcome some manufacturing issues of cost, effectively integrating the DRAM onto logic chips. Currently, ASIC vendors can incorporate blocks of up to about 64 Mbits. Expect that number to quadruple over the next year so that the ASIC can provide the total system solution, perhaps eliminating entirely the need to use off-chip memory.
>LARGER AMOUNTS OF MIXED-SIGNAL CIRCUITRY in the form of phase-locked loops, ADCs or DACs, and even some RF circuit functions will be integrated on mostly digital ASICs. Many companies are also considering the use of silicon-germanium technology to implement RF front ends on the complex ASICs that can operate at frequencies of 5 GHz and higher, thus allowing the ASICs to implement functions such as 802.11a wireless local-area networks (LANs) and other wireless interfaces.
>ASIC PACKAGE PIN COUNTS will continue to increase in 2003, with some devices requiring over 2000 pins. But in 2004, the package pin counts could start to decrease significantly as designers gain experience in leveraging embedded memory and high-speed serial interfaces. By embedding the memory, they can eliminate the data and address bus pins, and just a few high-speed serial channels can replace 32-bit and wider buses.
>POWER CONSUMPTION WILL START TO DROP as designers find more effective ways to lower power via clock gating and other techniques, as well as new circuit approaches to better leverage supply voltages that go below 1.1 V. Expect the next generation of ASICs to operate at supply voltages of 0.9 V as design features shrink to 90 nm and smaller.
>MASK COSTS WILL CONTINUE TO ESCALATE for multimegagate chip designs, moving past the $1 million per set mark. At the same time, nonrecurring engineering costs and test costs will also increase.