Electronic Design

Digital PLL Perks Up Performance In T1-E1, Other TDM Apps

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP filter in the PLL's loop filter to greatly improve stability and reduce jitter. Loop-filter bandwidths of 1.8 kHz and 922 Hz are available with the ZL30109.

Designed by Zarlink Semiconductor, this chip fits use in digital-subscriber-line access multiplexers (DSLAMs), Voice over Internet Protocol (VoIP) gateway and private-branch exchange (PBX) systems, and almost any time-division multiplexed (TDM) bus system. Its 19.44-MHz output also suits it for synchronous digital hierarchy (SDH) line cards.

The ZL30109 accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, or 19.44 MHz. The reference may be an external clock oscillator or a crystal. In turn, the device provides a wide range of synchronized outputs, including 1.44, 2.048, 16.384, 19.44, and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz. It generates five styles of 8-kHz framing pulses and 2-kHz multiframe pulses.

As a carrier-class timing control device, the ZL30109 must ensure continued operation during network disruptions or upgrades. The DPLL continuously monitors the input reference clocks and provides hitless reference switching upon detection of a bad or failed reference clock. It also maintains a stable and reliable output clock in the presence of network or intra-system jitter and wander conditions.

If the source of synchronization is temporarily lost, the ZL30109 automatically switches into holdover mode and continues to generate output clocks based on data collected from past reference signals. In addition, the device has a holdover frequency accuracy of 1.5 × 10­7. It includes lock, holdover, and selectable out-of-range indication.

Jitter performance is less than 0.6 ns p-p intrinsic on all output clocks and less than 24 ps rms intrinsic on the 19.44-MHz output, which complies with OC-3 Sonet and STM-1 SDH jitter specifications. The ZL30109 also meets all related requirements of Telecordia, ITU-T, ETSI, and ANSI.

The ZL30109 comes in a 10- by 10-mm, 64-pin TQFP. Cost is $13.50 in 1000-unit quantities.

Zarlink Semiconductor
www.zarlink.com

TAGS: Digital ICs
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