Electronic Design

DSOs Reveal Serial I/O Secrets

New probes and software simplify standards compliance.

Engineers who design the latest high-speed serial-data products based on standards such as PCI-Express, Serial ATA, Ethernet, XAUI, Fibre Channel, InfiniBand, and Serial Attached SCSI must jump a number of hurdles to prove that those products conform with the standards.

Early in the development cycle, that means testing the physical layer (PHY) using pseudorandom bit sequences or repeating test patterns to ensure signal integrity and timing stability.

After ensuring PHY compliance with pseudorandom sequences and test patterns, engineers use 8b/10b coded character sequences to debug system-level issues. Much of this work takes place in the protocol domain as higher levels of communication structure and application software are brought online.

Yet problems may still crop up in the PHY—the link-layer domain, where signal integrity and data integrity converge. Even the data on a well-designed PHY may be degraded by faulty transmission logic or signal corruption due to data-dependent crosstalk or power plane bounce. Such effects may manifest themselves at a character, word, or higher protocol level, but something in the physical design causes them.

To facilitate development, standard verification, and hardware troubleshooting, Tektronix has introduced the fastest real-time digital storage oscilloscopes (DSOs) yet. The 12-GHz TDS6124C and the 15-GHz TDS6154C can store up to 64 million sample points, which may be acquired at the full 40-Gsample/s rate (Fig. 1). Primary and delayed sweeps can be triggered on everything from conventional trigger events to data words as well. In fact, more than 1440 combinations of trigger choices are available. At the same time, optional software takes much of the knob-spinning out of matching performance to standards criteria.

The front ends in both DSOs have the same 12-GHz bandwidth, and both follow that with similar finite impulse response DSP filters. However, the 6154 also uses the filter to extend the scope's effective bandwidth to 15 GHz (see the table).

To interface with the real world, companion differential probes have tips that can single out one lone ball on a dense ball-grid-array IC package or fit between the tiniest of surface-mount components (Fig. 2). The P7313 probe has a bandwidth of greater than 12.5 GHz and 25-ps 20%/80% rise-time capability. Their dc input resistance is 50 kO per side, or 100 kO total. Their ac loading is greater than 250 O.

To allow the probe tips to reach into tiny places, the P7313 combines a traditional passive-probe topology with an active probe amplifier in the body. The passive probe tip resides on a flexible coaxial assembly that extends from the amplifier housing. Tektronix also provides interchangeable solder-in, handheld, and fixtured specialty-tip assemblies called Tip-Clips.

To meet the technical criteria for capturing the high harmonic details of serial signals, 12- and 15-GHz bandwidths plus 40-Gsample/s sampling rates are essential. It's desirable to capture at least the third, and preferably, the fifth harmonic. Transitions in 6.0-Gbit/s Serial ATA III have now pushed that frontier to 15 GHz.

Jitter analysis, modulation and clock measurements, and various signal quality metrics all need deep memory to support the analyses called out in standards and specs. Measurements based on the pseudorandom bit stream exercise known as PRBS23-1 and spread-spectrum clock (SSC) modulation (used for SATA II measurements among others) both require long record length.

For example, PRBS23-1 generates 8,388,607 bits of data, amounting to 56.8 million samples. SSC captures 10 cycles of a slow modulation envelope while sampling the data at full sample rate. This test accumulates more than 12 million samples.

At 40 Gsamples/s, even a 2-Mpoint memory would only store about 50 µs of full-bandwidth signal data. The TDS6000C scopes can be equipped to store 64 million sample points acquired at the maximum 40-Gsample/s rate. That's the equivalent of 1.6 ms of data.

The optional PTD Protocol Trigger And Data Decoding software module makes it possible to decode and simultaneously display protocol-level information and PHY signaling. In conjunction with the serial pattern triggering, users can also trigger on protocol primitives and characters in real time up to 3.125 Gbits/s. PTD is designed for 8b/10b encoded signals. For these scopes, PTD also provides a general-purpose, 40-bit pattern trigger for non-8b/10b encoded links such as FG-DIMM.

With PTD, designers can set the scope to trigger conditionally on up to four consecutive 10b characters specified individually or selected from a predefined list of primitives. The instrument also responds to character or disparity errors to efficiently isolate corrupted traffic.

The trigger responds immediately to incoming data. In other words, triggering is a real-time function rather than a post-processing operation. Thus, it's possible to trigger on a defined fault condition rather than capture an arbitrary window and search it.

Decoding is automatic. The outcome of an acquisition is a detail-rich display of character- and word-level information, along with fully annotated waveforms. Information includes signal behavior and 10-bit symbol content, characters and their data or symbolic values, and word-level information like primitives and higher structures.

Views are synchronized so that effects in one can be compared with conditions in another. For instance, a disparity error flagged in the word view can be traced to a corresponding character code and physical signal activity.

Other software packages are available. The TDSRT-Eye Serial Data Compliance & Analysis package provides automated eye diagram measurements, standard-specific parametrics, standard-specific application modules, and user-customized masks and measurements. The TDSJIT3 Jitter and Timing Analysis package complements the TDSRT-Eye package with a set of advanced jitter-measurement and display functions.

These scopes use sixteen 8-bit, 5-Gsample/s, four-way pipelined analog-to-digital converters with associated front ends built on IBM's 0.18-µm 7HP silicon-germanium process. Their npn fT measures 100 GHz, and their fMAX is 120 GHz. The TDS6124C costs $100,000 and the TDS6154C costs $125,000.


TAGS: Digital ICs
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