Claimed as the industry’s highest performance DSP for consumer multimedia and mobile applications, the ZSP500 is the latest addition to the company’s open architecture ZSP digital signal processor cores. Based on the ZSP second-generation G2 superscalar architecture, the ZSP500 has been designed to offer high performance and low power consumption at a low cost. Architectural innovations of the ZSP500 include an eight-stage pipeline, scalable program and data paths, and user-configurable memory architecture. Operating at up to a 400 MHz clock rate, the core can achieve 1,600 MIPS of peak processing power and 800 million sustained MACs/second. An enhanced instruction set produces higher code density and a more efficient execution of key algorithms. In addition, designers can incorporate customized instructions for their target application. Other features of the ZSP500 include: fabrication using 0.11-µm technology; dual multiplier-accumulators; three ALUs—one 40-bit and two 16-bit; orthogonal instruction set; dual 32-bit data interfaces with dedicated address generation; configurable memory space; 24-bit instruction and data address range; automatic and software controlled power management; and bi-directional co-processor and hardware acceleration interface. Debugging and embedded real-time trace capabilities are said to provide optimal capabilities for rapid debugging of integrated hardware and software solutions. The ZSP500 can be used with the company’s new RapidChip semiconductor platform for fast time-to-market SoC designs. The core is available now for licensing in both synthesizable RTL and hard macro versions. For more details and pricing, contactLSI LOGIC CORP., Milpitas, CA. (866) 574-5741.
Company: LSI LOGIC CORP.
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