Designed from the ground up, the CoolFlux DSP core requires less than 0.1 mW/MHz when implemented with 130-nm design rules and powered by a 1.2-V supply. An alternate implementation on a 180-nm process consumes less than 0.2 mW/MHz when powered by a 1.8-V supply. On the 130-nm process, the core has a top operating clock frequency of 175 MHz. With the 180-nm process, the top speed only drops to 135 MHz.
CoolFlux, developed by Philips Digital Systems Laboratories, consists of a dual Harvard architecture engine with 24-bit datapaths, two 24- by 24-bit signed multipliers, three ALUs, and four 56-bit accumulators (see the figure). Requiring just 43 kgates, this space-saving DSP core still can incorporate extensive power-management support, including Stop and Restart instructions. It also packs extensive addressing modes, such as modulo protection and bit reversal capabilities, saturation and rounding units, and support for zero-overhead loops (nested up to four levels).
The RISC-like 32-bit instruction set contains commands for control operations as well. As a result, the core can perform both signal processing and control functions, potentially eliminating the need for a separate dedicated controller. Three maskable, low-latency interrupts and DMA ports for program and data memories populate the core as well. Each of the four memory spaces (Program, X, Y, and I/O) features a 64-kword address range.
Philips developed tool support for the processor in collaboration with Target Compiler Technologies. It includes a C compiler, assembler, linker, and graphical debugger. An extensive software library for audio decoding and advanced sound enhancement algorithms supports the DSP core.
Though the core is Philips' creation, it will be distributed through the Synopsys DesignWare Star IP library, making it available to over 25,000 library users. License fees are negotiated on an application-by-application basis.
Philips Digital Systems Laboratories