Electronic Design

DSP Speed Bump Helps Boost Channel Densities

By pushing max clock speed from 400 to 500 MHz, the MSC8122 and MSC8126 quad core DSP chips can implement higher channel densities in codecs for wireless basestations.

At the higher clock speed, these quad-core devices from Freescale Semiconductor increase performance by 50% compared to the first-generation MSC8102. They deliver the equivalent of a single DSP core running at 2 GHz with throughput of 8000 million multiply accumulates (MMACs). When running at 500 MHz, the MSC812x DSPs raise channel densities. This reduces system costs in packet telephony, wireless transcoding, wireless basestations, video infrastructure, and other applications.

The MSC8126 includes both a Turbo and Viterbi coprocessor. The Turbo engine can support 20 384-kbit/s channels or four 2-Mbit/s channels when running at 500 MHz. The channels comply with 3GPP and CDMA2000 standards. The Viterbi coprocessor supports 400 3GPP 12.2-kbit/s AMR channels and performs fully programmable feed-forward channel decoding.

Both quad-core DSPs share 476 kbytes of level 2 cache. They also include a 16-channel DMA engine and the four SC140 DSP cores. Each core packs dual multiplier-accumulators, 16 kbytes of internal cache, and a 224-kbyte level 1 memory.

The 500-MHz MSC8122 and MSC8126 will sample in January. Full production is planned for April 2005. Versions running at 400 and 300 MHz are sampling now, with production expected in January. In lots of 10,000, the MSC8122 at 500 MHz costs $191 apiece. The 500-MHz MSC8126's price hasn't been finalized.

Freescale Semiconductor Inc.
www.freescale.com/dsp

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