Dual-Core Cortex-M4 And M0 MCU Redefines Digital Signal Control

Eindhoven, The Netherlands: The LPC4000 family offers the first asymmetrical dual-core digital-signal-controller architecture featuring ARM Cortex-M4 and Cortex-M0 processors, claims NXP Semiconductors. DSP and MCU applications now can be developed within a single architecture and development environment. With the dual-core architecture, customers are able to develop a range of applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories, and embedded audio.

According to the company, microcontroller designers who want more efficient ways to tackle math-intensive algorithms, and DSP designers who feel constrained on peripherals, stand to benefit from the LPC4000’s architecture.

The controllers’ Cortex-M4 processor combines microcontroller features, such as integrated interrupt control, low-power modes, low-cost debug and ease of use, with high-performance digital-signal-processing features (e.g., single-cycle MAC, single-instruction multiple-data techniques, saturating arithmetic, and a floating-point unit).

An optimised 256bit-wide flash-memory architecture reduces power consumption with minimum memory fetches while maximising the performance of the Cortex-M4 processor. A dual-bank architecture provides up to 1MB of flash memory for safe reprogramming and flexible memory partitioning. Moreover, there’s 264kB of SRAM.

A Cortex-M0 subsystem processor offloads many of the data-movement and I/O-handling duties that can drain the bandwidth of the Cortex-M4 core. Thus, the Cortex-M4 can concentrate fully on crunching numbers for digital-signal-control applications. An asymmetrical dual-core gives developers the power, cost, and system complexity savings of a one-chip solution, and makes it easier to partition the software.

Configurable peripherals available on the LPC4000 include a state configurable timer, an SPI flash interface, and a serial GPIO interface. The state configurable timer subsystem consists of a timer array with a state machine, which enables complex functionality such as event-controlled PWM waveform generation, ADC synchronisation, and dead-time control.

The SPI flash interface provides a seamless, high-speed, memory-mapped connection to virtually all SPI and quad-SPI manufacturers. The serial GPIO, available for the first time on the LPC4000, gives developers the flexibility to interface to any non-standard serial interface or mimic multiple standard serial interfaces (such as I2S, TDM for multichannel audio, I2C, and more).

Additional peripherals on certain members of the family include two high-speed USB controllers, an on-chip high-speed PHY, a 10/100T Ethernet controller with hardware-enabled TCP/IP checksum calculation, and a high-resolution color LCD controller.

Standard features on all members of the LPC4000 family include 32kB ROM containing boot code and on-chip software drivers, AES-128 decryption (encryption is available on some members of the family), eight-channel general-purpose DMA (GPDMA) controller, and two 10-bit ADCs and 10-bit DAC with a data-conversion rate of 400ksamples/s. There are also a motor-control PWM and quadrature encoder interface, four UARTs, two Fast-Mode Plus I2C, I2S, 2 SSP/SPI, smart-card interface, four timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256bytes of battery-powered backup registers, and up to 146 general-purpose I/O pins.

Engineering samples of the NXP LPC4000 will be available at the end of the month, with full commercial distribution starting in December.

NXP

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