Electronic Design

EDA Roundup

A low-power SoC design collaboration between ARM, Artisan Components, National Semiconductor, Synopsys, and UMC culminated in a comprehensive technology demonstration for the ARM926EJ-S processor. The combined power-saving capabilities of the technologies that make up the demonstrator are expected to result in energy savings of up to 60%. The Ultra technology demonstrator is implemented in UMC's 130e Fusion 130-nm process. It uses Synopsys' Galaxy design platform and DesignWare IP library for AMBA bus and peripheral IP. Artisan's Metro platform of IP products is the source for underlying physical IP. Visit www.arm.com, www.artisan.com, www.national.com, www.synopsys.com, and www.umc.com for further information.

OCP-IP has four new members: 3plus1 Technology is a fabless semiconductor maker. AccelChip provides algorithmic synthesis and semiconductor IP for DSP designs developed in Matlab. Hantro Products brings to the table MPEG4 video codecs. And, Synfora produces tools that synthesize RTL from C-language design descriptions. The Open Core Protocol International Partnership promotes the Open Core Protocol as a socket standard for IP reuse and decreased design risk. For more information and membership information, visit www.ocpip.org.

TAGS: Digital ICs
Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish