EDA Vendors Line Up Behind Altera's Stratix III FPGAs

Three major vendors of FPGA front-end implementation flows have announced support for Altera's Stratix III devices. Built on TSMC's 65-nm process, Stratix III FPGAs are said to deliver 50% lower power, 25% higher performance and 2x the density compared to previous generation Stratix II devices.

Aldec Inc. is rolling out its System Verification Environment (SVE) for Stratix III; the environment supports all aspects of system-level design, development, and verification. Included is a common-kernel HDL simulator, a set of online debuggers, code coverage, cross-probing tools, and an integrated server-farm manager for automatic verification of ultra-large designs.

From Magma comes Stratix III support in the form of its Blast FPGA synthesis tool. Blast FPGA for Stratix III is built on top of the devices' physical framework, creating both a starting point for placement optimization and accelerated timing closure.

For its part, Mentor Graphics has also announced synthesis support for the new FPGA in the latest revision of Precision Synthesis. Beta support for the devices is available now with production support available with the release of Altera's Quartus II v6.1 software suite.

Last but not least, Synplicity's Synplify Pro FPGA and Synplify DSP synthesis tools now offer Stratix III support. Synplify Pro accepts Verilog or VHDL as input and compiles, optimizes, and maps the RTL into efficient netlists for the Stratix III silicon. It also generates constraints in SDC format for passing on to Altera's Quartus II backend. Synplify DSP users gain a complete algorithm-to-implementation flow for the Altera FPGAs.