Electronic Design

Eradicate Hardware And Software Bugs On Multicore SoCs

Able to debug complex SoC designs, this powerful emulator leverages a common JTAG port to diagnose software running in multiple deeply embedded processors.

System-on-a-chip (SoC) designs have emerged as system-critical solutions to reduce size, complexity, power, and cost. Additionally, technology improvements over the last few years have allowed SoC solutions to grow more complex. Relatively straightforward combinations of a single CPU, some memory, and some custom functions have become highly complex SoCs with hundreds of processor blocks. As designers craft these ever more complex single-chip systems with multiple processor cores, debugging the software for these embedded processors becomes increasingly more difficult.

Monitoring one core at a time provides little insight when multiple cores must interact. Designers need a debugging capability that lets them concurrently monitor multiple software streams that execute on multiple, disparate processor cores--CPUs, DSPs, custom functions, and so on. Moreover, the tool must be scalable to permit the debugging of literally hundreds of cores that can now reside on a single chip.

Embedded Performance Inc. (EPI) has developed such a debugging system. It provides support for a wide range of processor types, as well as the ability to scale up to handle ever-increasing numbers of cores on-chip. Known as Multidimensional Scaling Support (MDS2), the technology addresses the ongoing multidimensional scaling of SoC designs.

The basic system consists of a host computer that runs the debugging software, a serial or Ethernet interface to the MAJIC pod, which measures just 2 by 6.5 by 7.5 in., and the JTAG interface to the SoC under scrutiny (Fig. 1a). The MAJIC pod is an intelligent debug probe that incorporates the MDS2 technology (Fig. 1b). In the MAJIC pod is a microcontroller with its own local SRAM, Flash memory, JTAG control engine, trigger logic, and Ethernet interface. The MDS2 software supports multitap devices, multicore chips, multiarchitecture environments, multisession debugging, multicontext CPUs, and on-chip trace buffers.

To support complex designs, engineers at EPI crafted a combination of software tools and a multiprocessor advanced JTAG interface controller, the MAJICMX. Together, they form a powerful and scalable solution for multicore SoC debugging. The tools will work with various debug software solutions, most notably, EPI's own EDB host-based debugging software. However, the tools will also integrate well with other debug software that follows industry-standard application programming interfaces (APIs). Some of those interfaces include MDI, RDI, Tornado, and the Microsoft platform builder (Fig. 2).

In addition to handling multiple processor cores, the tools let designers debug multithreaded software by supporting hundreds of multiple-context operations. Multisession support lets designers run multiple debug sessions concurrently using the same MAJICMX and debug interface to the SoC. This feature can be used to support debugging multicore and/or multiarchitecture applications.

Multiple debuggers can employ the same MAJICMX probe to concurrently communicate with individual cores on the JTAG chain. Each debugger can target a different core and simultaneously communicate with the selected cores. The debuggers could even reside on multiple host computers and connect to the probe via the Ethernet port.

With the MDS2 software, designers will be able to nonintrusively and selectively communicate with the on-chip cores through a JTAG interface. For most on-chip debug facilities, the MDS2 won't use any target memory, so it requires no porting to the target system. Each processor family that the tools support comes with its own configuration kit that provides the architecture-specific information necessary for the tools to complete processor control. This way, designers can start, stop, and single-step each core. Additionally, they can read and write to registers, memory, and system I/O lines, as well as download code to target RAM.

To use the MDS2 technology, cores in the SoC must include some circuitry that lets the external probe access the CPU, DSP, or other core logic and registers. This includes support for traditional debug tasks typically associated with an old-fashioned target monitor. Luckily, when they're delivered from the intellectual-property suppliers, the cores already contain much of what's required.

The on-chip debug access and control circuitry must allow access to the target memories, caches (both on- and off-chip, if applicable), internal registers, coprocessor registers, and other processor status bits, like program counter and call stack. Ideally, the debug circuitry would also include DMA to target memory. This will facilitate the downloading of programs prior to testing.

The debug circuitry should also allow the setting and management of breakpoints. In the optimal case, the core would support hardware breakpoints, as well as traditional software breakpoints and a single-step capability. A number of good standard on-chip debug specifications are already available, which the MDS2 tools can leverage--EJTAG, Nexus, EmbeddedTrace, N-Wire, and others. Of these, the EJTAG 2.0 specification provides a good, basic guideline for access and control capabilities.

Beyond the access and control functions, the SoC must include some type of communication port that's independent from the I/O ports used by the application program. Most digital SoCs now incorporate JTAG for boundary-scan testing. Therefore, that port can be used to access the on-chip debug logic. Lastly, the core blocks must include some type of on-chip trace circuitry because it's impractical to bring out all of the signals needed for tracing each processor's execution flow. The on-chip circuits must encode the trace information into a manageable number of signals and then bring the data off-chip at a manageable data rate.

Data Extraction Challenges
As SoC devices scale upwards in complexity and performance, extracting uncompressed data from a chip be-comes more challenging. It would require using a significant number of I/O pins. Or, the data would need designers with lots of patience, as a large amount of trace information would have to be transferred to memory in the probe pod.

To reduce the quantity of data that has to be transferred and minimize the amount of memory needed to hold the trace information, designers at EPI worked with the various processor suppliers. They developed an encoding scheme that employs a small amount of on-chip trace memory and still provides meaningful execution trace information. Both the Intel XScale and Lexra LX8000 series cores use this type of encoding scheme. This permits the trace data to come out of the cores and be transferred over the JTAG port to the MAJIC pod.

The MAJIC JTAG port can only handle multiple cores if the JTAG tap controller in each core is connected in a chain to a common JTAG interface on the SoC. Currently, the MAJIC hardware supports only JTAG communications to the on-chip debug circuitry. But the MAJICMX version will be able to interface to a wide variety of communications interfaces.

Data transfers over the JTAG port can take place at clock speeds from dc to 40 MHz. The MAJIC pod is equipped with both an RS-232 serial interface (1900 bits/s to 115.2 kbits/s), and a 10/100-Mbit Ethernet interface, to connect to the host computer that runs the main debug tools. The Ethernet interface lets the pod be used in either a shared or remote configuration. Five status indicators on the pod show the operational status of the emulator: power, status, run, connect, and Ethernet.

Once the MAJICMX pod is connected and the host computer is fired up and running the debug software and MDS2 tool suite, the pod is ready for action. For each processor core family on the SoC the tools will diagnose, a configuration kit must be installed. In most cases, one MAJICMX can have any number of configuration packages installed. Configuration kits will initially be available for ARM, MIPS, and Intel XScale processors. The kits will include support for the ARM9E and the Lexra LX5280 MIPS core, which both include some DSP capabilities. DSP core support will follow later this year. It will include cores from Texas Instruments, the DSP Group (Oak, Teak, Palm), Philips (Real16 and Real32), and the LSI Logic ZSP.

Price & Availability
The MAJICMX basic offering consists of the pod and one configuration kit (one CPU/DSP core family). It has a base price of $3995. A utility disk also comes with the kit. It includes a wide variety of initialization files, demo programs, a command-line debugger, and RDI/MDI dll files that will allow an RDI- or MDI-compliant debugger to work seamlessly with the pod. Additional configuration "kits" for various processors range in price from $1495 to $2995, depending on the processor.

A more complete bundle, which includes the company's host-based EDB source-level debugger, sells for $4995. In both cases, the user must provide a host PC to run the MDS2 software and debugger. The license for the EDB software requires the purchase of a license for each debug seat. For example, a customer designing an SoC with four ARM cores would license the MAJICMX with a CKM-01AM configuration kit, plus the EDB-ARM source-level debugger with four single-user licenses per debug station. (Or, a customer could purchase a four-user network floating license.) Additional EDB seats would cost $1995 each.

Embedded Performance Inc., 606 Valley Way, Milpitas, CA 95035; Lyle Pittroff, (408) 719-5600; www.epitools.com.

TAGS: Digital ICs
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