Electronic Design

FPGAs Boot In A Flash

According to Lattice Semiconductor, the company's LatticeXP2 family represents the industry's first line of single-die, 90-nm, nonvolatile FPGAs. Based on the previous generation, these devices offer up to 40k lookup tables, up to 885k of embedded dual-port memory, up to 12 DSP blocks, and up to four phase-locked loops (PLLs).

The 1.2-V devices also boost performance by 25% and use up to 33% less static power compared to their predecessors in a package as small as 8 by 8 mm. But perhaps their most impressive feature is their die-integrated flash, which stores the device configuration during power-off, and SRAM, which stores the configuration during power-up (Fig. 1).

After power is applied, configuration data is transferred to the SRAM in a massively parallel operation so the "boot" or "wakeup" time is about 1 ms. Devices that provide SRAM and nonvolatile memories as separate dies in the same package (hybrid devices) or in separate packages offer boot times of 120 ms or higher, making integration a potential issue for protocols requiring reduced wakeup times.

Also, storing and transferring the configuration information on-die eliminates the typical security concerns that plague two-chip solutions. The family's additional security measures include a security bit to prevent readback of the flash or SRAM and AES128 programming data encryption with on-chip key storage (Fig. 1, again). A flash lock feature prevents unauthorized programming. There's even a one-time programmable node.

"With the closest announced non-volatile FPGA products using a 130-nm process technology, the Lattice 90-nm embedded flash process used for the LatticeXP2 products is the most advanced process in use for nonvolatile FPGAs," said Gordon Hands, director of Strategic Marketing for Lattice.

"Unlike stacked-die hybrid devices, our 90-nm embedded flash process provides designers with all the advantages of true nonvolatility: flexible logic, the smallest footprint, the highest security, and instant-on. Hybrid devices provide only moderate security and no instant-on capability," he said.

Lattice has also revisited the process of in-field updates with its TransFR technology, which enables new configuration information to be loaded to the flash. At that time, the I/Os may be locked in any desired state, whereas the common update method requires the I/O pins to be tri-stated during in-system updates. The process continues with the transfer of the configuration information from the flash to the SRAM. Then, the device regains control of the I/O pins.

Of course, reliability becomes a concern when configuration transfers can't be completed due to some sort of system or device glitch. That's why the LatticeXP2 family offers the option of using an external SPI-based boot memory, including the "gold configuration" that's used when a bitstream error is detected.

Lattice also gave its ispLever development tool suite a face lift. Its improvements aid in speed and utilization enhancements. It features a much-improved power calculator (Fig. 2). And, the design analysis tool includes a complete logic analyzer that supports complex trigger sequences.

Samples of the 17K LUT LatticeXP2-17 are available now. Lattice plans to bring the entire family to market this year and expects the LatticeXP2-17 to be available in full production next year with pricing as low as $12.00 in 100,000 unit lots.

Lattice Semiconductor
www.latticesemi.com

TAGS: Digital ICs
Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish