Electronic Design

FPGAs, Structured ASICs Bring Home The Bacon

FPGAs and structured ASICs are like Baby Boomers. They continue to look for ways to improve their position in life while reaping nice raises every year (in the form of revenue boosts). They're also more liberal than their elders. And, they continue to try to leave a mark on society. The main difference is that FPGAs and structured ASICs aren't looking to retire anytime soon.

On the contrary, FPGAs and structured ASICs look to expand in markets like automobile infotainment. There's also a push to move more functionality traditionally reserved for DSPs into FPGAs, such as applications that require several channels like wireless basestations.

Companies like Altera, eASIC, and Xilinx will all offer 65-nm process technology-based devices. So, it will be interesting to watch the industry this year and see how much more of a system gets implemented in FPGAs and structured ASICs.

State Of The Union
According to research firm Gartner, FPGAs will grow 18% this year and maintain the highest compound annual growth rate (CAGR) over the next few years compared to ASICs and ASSPs (Fig. 1). This suggests that FPGAs will grab more market share from both sectors.

"Expect FPGAs to continue to increase market share versus ASICs as more applications adopt FPGAs and as more system functionality is implemented on FPGAs due to the high development cost of ASICs," says Danny Biran, vice president of product and corporate marketing at Altera (see "Let Innovation Resonate Throughout The Industry."

"There are two fundamental reasons why FPGAs move to the heart of the system and continue to gain market share versus ASICs," Biran says. "First, as ASIC development cost goes up, it is difficult to justify the development of an ASIC for many market segments, simply because the ROI (return on investment) isn't there. Secondly, current performance and density levels of FPGAs meet the requirements of many more high-end applications, while the price of low-cost FPGAs meets the requirements of many cost-sensitive applications."

The View At 65 nm
Good evening folks, this is your captain speaking. Today's cruising altitude will be 65 nm. If you look out to the right of the industry, you can see the Xilinx Virtex-5, while off to the left we're approaching the Altera Stratix III.

Xilinx was the first to market with a 65nm offering, and its Virtex-5 devices are well known throughout the industry. They have up to 330k logic cells and 1200 I/O pins. Also, they support over 60 I/O standards and RocketIO serial transceivers, and they include a built-in PCI Express endpoint and Ethernet media-access controller (MAC).

The Virtex-5 devices, which can implement differential interfaces up to 1.25 Gbits/s, help keep signal integrity in check using digitally controlled impedance for active I/O termination. Designers may choose one of several IP controller and DSP cores, which can be integrated using power-saving features. By now, there are many product reviews, and Xilinx has a complete set of collateral available on its Web site.

The new kid in town, expected to arrive in the third quarter of this year, is Altera's 65-nm Stratix III device. It offers more control over power consumption using Programmable Power Technology (PPT). It also offers more design flexibility than past models.

PPT maximizes the performance of high-speed paths while minimizing power usage elsewhere. Each logic, DSP, and memory block is analyzed to determine if it should be placed in high-speed or lowpower mode. PPT is possible thanks to PowerPlay, a relatively new feature of the Quartus II tool that automatically analyzes the design to determine critical path signals that demand high performance. The decision to place a block in highspeed or low-power mode is based on timing constraints and the clock slack at that block.

Stratix III also can set the core operating voltage to 1.1 or 0.9 V. Designers can choose 1.1 V for applications that need higher performance and 0.9 V for applications that require minimal power consumption. Altera is the only company currently offering PPT and a settable core voltage. Furthermore, the Stratix III provides a very simple gateway to Altera's HardCopy structured ASICs, which are low-cost, functionally equivalent, and pincompatible with Stratix III.

When it comes to signal integrity, Stratix III FPGAs offer a high power- and ground-pin to userI/O-pin ratio, along with optimized signal return paths, adjustable slew rates, staggered output delays, and calibrated on-chip terminations. These features will help reduce potential issues with simultaneously switching output noise (SSO or SSN).

To DSP Or Not To DSP
FPGAs will encroach further into DSP territory by dangling a very tantalizing carrot in front of engineers (especially those dealing with multiple channels of high-speed data): hundreds of fixed-point multiplications per clock cycle that pop out several times faster than the fastest DSP (comparing pure hardware to pure software implementations). This makes some applications once handled by DSP farms ideally suited for the latest FPGA offerings.

The main issue going forward for FPGA vendors is to offer a tool set that translates algorithms into efficient hardware implementations, helping bridge the gap between complex functionality. The underlying issue involves taking a complex algorithm created in hours or days using MatLab and translating it into a hardware implementation utilizing an HDL like Verilog or SystemC.

Often, the end result takes an order of magnitude longer to reproduce and tweak the same algorithm using an HDL, and implementation will look nothing like an algorithm and instead come out as a jumbled mess. Yet the prospect of handling several channels of data using a single FPGA, with room left over for a general-purpose processor and other functional blocks, may be enough to overcome the design time woes. In some cases, an FPGA or massively parallel processor may be the only way to go.

"Where parallelism is important, FPGAs are better than DSP processors," says Altera's Biran. "Processors have hit a wall in what they can get from process improvement, leading processor companies to move toward dual-core and multicore implementations. FPGAs are inherently built of many processing elements that can operate in parallel, which is what the processing platforms of the future need."

Revised Forecast For Structured ASICs
A few years ago, Gartner predicted a threefold increase over a two-year period in structured and platform ASIC revenues, going from $473 million in 2006 to $1.45 billion in 2008 (Fig. 2). The revised forecast shows revenues roughly doubling over the next three years, winding up around $828 million in 2009.

While this isn't as good as tripling revenue, this jump still far exceeds the rest of the semiconductor industry, which is expected to grow around 20% over the next three years. So why isn't the outlook as positive as originally forecasted?

The general feeling of folks in the know is that the trust still isn't there, as there's just too much risk revolving around structured ASICs. After all, quite a few players in this market are relative newcomers compared to the big hitters in the ASIC foundry space, such as IBM and TSMC. Lastly, structured ASICs do tend to lag behind somewhat in process technology offerings.

But eASIC has eliminated all objections by offering a zero-NRE structured ASIC with no minimum order quantity and a short turnaround time. In fact, it will have an early offering of a 10 million-gate, 65-nm structured ASIC later this quarter called the Nextreme II. For now, the 5 million-gate Nextreme NX5000 is available with a plethora of drop-in intellectual property (IP) and nearly 6 Mbits of RAM.

The interconnect is customized through a single via layer generated using a maskless electron beam lithography approach called eBeam Direct-Write. This method eliminates the need for custom masks, removing the associated tooling cost and shortening turnaround time. This unique approach lets eASIC share wafers among customers or projects by printing different patterns on the same wafer, meaning no minimum order quantity. Also, to mitigate risk, eASIC uses Fujitsu's 90-nm process technology.

"The structured ASIC market is demonstrating a normalized cycle from hype to ripe, where the message of ‘the new trend in town' gained momentum and was spread from the vendors to the media and analysts to the users' community," says Ronnie Vasishta, CEO of eASIC.

"There is an undeniable critical need and a large potential market for a structured or platform ASIC solution. Now, we are moving from the heavily publicized domain to the normal course of business where features and benefits win—in particular, price, power, low risk, and fast time to production. This requires innovation and a truly disruptive technology," Vasishta continues.

"The window of opportunity is wide open for a breakthrough structured ASIC that can meet the customer's critical needs and diminish the challenges of deep submicron design and manufacturing," he notes.

So if the semiconductor industry has a less than stellar year, no one will be able to point the finger at FPGAs or structured ASICs as the cause.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish