FPGA silicon technology has undergone quite a metamorphosis since emerging on the scene in the 1980s, and its supporting design technology has necessarily evolved as well. Not entirely surprisingly, though, the design community that's eager to embrace advances in FPGA capacity and performance has been more sluggish in adopting corresponding design technology advances. The reasons for the disparity are nothing new: An existing design methodology can be like an old, favorite pair of shoes. In the case of FPGA design, ASIC-style methods are the old pair of shoes whose time has come to go to the red-tag sale.
FPGA-aware design technology is not really new—it's just re-emerging in response to the demands of the design community and the silicon's capabilities. When FPGAs first appeared, they were relatively small and simple, and FPGA vendors offered design tools that provided for the physical implementation of their own devices. So the original design solution was FPGA-aware—tailored to the specific architecture and vendor. Later, ASIC EDA vendors, eager to serve the growing community of FPGA designers, gradually edged out the FPGA vendors in the front-end design space. At this point, the design technology moved away from being FPGA-aware, and instead retrofitted the ASIC flow for use in the FPGA space. This was adequate for the size and complexity of the programmable offerings at the time, and for silicon technology in which logic dominated performance. But that was about to change.
With the rise in FPGA size, complexity, and performance, along with the increasingly dominant role of interconnect and placement in design success, the advantages of FPGA-specific design tools become more evident. The first step in differentiating the FPGA flow from its ASIC counterpart was in the area of mapping directly to FPGA-specific logic cells rather than through a generic library. Direct mapping offers improved area and performance over ASIC algorithms by taking advantage of the FPGAs built-in architectural features. As FPGAs evolved, they added a wide variety of special functions such as shift registers, RAM and DSP blocks, and direct mapping that takes maximum advantage of these blocks. However, even more is required to address today's problem of interconnect-dominated device performance.
To address timing convergence and designer productivity in interconnect-dominated devices, FPGA design technology took the next necessary step along the path of divergence from its ASIC counterpart. Timing estimation in the ASIC EDA realm operates under entirely different assumptions than that of the FPGA. After all, routing resources are not fixed in custom circuits as they are in FPGAs—it is adequate for ASIC algorithms to estimate interconnect delays based on the proximity of the logic elements they connect. For FPGAs, the realities of connecting logic elements are entirely different due to fixed routing resources. Thus, they instead require detailed knowledge about the FPGA architecture being targeted and its associated routing resources.
It's no longer possible to estimate FPGA timing without accurate placement and routing information, and this requires sophisticated FPGA-specific algorithms that are absent from ASIC EDA technology. Instead of proximity-based estimation and wireload models, new FPGA EDA technology that applies in-depth knowledge of specific FPGA architectures and performs placement and preliminary routing during synthesis (using graph-based timing estimation algorithms) is a new imperative for design success. By employing such technology, FPGA developers not only maximize their productivity by avoiding time-consuming iterations, but also realize the full performance potential of today's advanced FPGA technology.