EE Product News

Hybrid ASIC Chisels Down SoC Development Costs

Configuring a structured ASIC as IP on a standard-cell device, the company's Hybrid ASIC forecasts rapid and economical system-on-chip (SoC0 development with significant savings in non-recurring engineering and tooling costs. According to the company, its Hybrid ASIC provides the benefits of standard-cell and structured ASICs without tradeoffs and promises turnaround times for logic changes as short as six weeks. Typical applications include video compression or data encryption for users hoping to integrate different compression or encryption schemes on one chip. It also suits the implementation of an ASIC with a pre-standard interface or algorithm. For these situations, variable design logic resides in the configurable structured ASIC area. The chip teams standard cell logic and I/Os, memory plus mixed-signal IP with a predefined configurable logic in a structured ASIC core and configurable memory. Users choose what functionality goes in the configurable portion of the chip and the company customizes a structured ASIC IP core in any shape or size from 50k to 2M gates. As the Hybrid ASIC is user specific, it can support up to 10M ASIC gates and 10 Mb of memory with a wide range of IP including PCI Express, USB 2.0 OTG, video DAC and ADC, synthesizable processors from ARM and Beyond Semiconductor, DDR/DDR2 PHYs, controllers, ands over 200 blocks of synthesizable IP. For more details, call CHIPX INC., Santa Clara, CA. (800) 952-4479.

Company: CHIPX INC

Product URL: Click here for more information

TAGS: Digital ICs
Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish