Electronic Design

Instruction-Set Extensions Let CPU Accelerate Key Operations

By integrating configurable logic into the datapath of a high-performance processor, designers at Stretch Inc. have crafted a CPU that combines a fixed instruction set and a way to create highly optimized custom instructions in hardware.

The S5000 software-configurable processor family combines the flexibility of the compilable Tensilica Xtensa RISC processor core and the programmable Stretch instruction-set extension fabric (ISEF) to create a processor that delivers an instruction set tailored and optimized for market-specific applications.

In typical multimedia applications, the S5000, when clocked at 300 MHz, can perform operations like sum of absolute differences for H.263 codecs in two-thirds the time of 600-MHz DSP chips from Texas Instruments.

Integrated into the RISC processor's datapath, the ISEF circuits extend the processor's instruction set (see the figure). Users can define new instructions using C or C++ code. Then, the Stretch software tools translate the code into logic configuration patterns that implement the custom instructions in the datapath.

Previous approaches that combined programmable logic on the same chip as the CPU didn't deliver as much performance. That's because they didn't incorporate such logic in the datapath. Instead, they used the logic to implement a more loosely coupled coprocessor to handle the desired operations.

Breaking new ground, the S5000 lets the configurable instructions replace complex instruction sequences with one command, accelerating many complex operations. Stretch plans initially to release three versions of the processor, the S5400, S5500, and S5610, which target different markets.

Designed for consumer multimedia applications, the S5400 packs a 10/100 Ethernet port, two FIFO buffers, and a DDR-333 32-bit SDRAM interface. It will cost about $35 each in 25,000-unit lots.

The S5500 suits medical instruments, office equipment, and professional video applications. It has double the number of FIFO buffers, a PCI-32 bus interface, and a DDR-400 64-bit memory interface. It will cost about $70 each in lots of 10,000.

The high-end S5610 adds a Gigabit Ethernet port, a PCI-X port, and a system address bus. It enhances the 64-bit memory bus with error-checking and correction. In 10,000-unit lots, it costs $100 each.

To support the instruction-set customization, Stretch offers a complete suite of development tools and includes a graphical integrated development environment ($900 for a single-user license) with the Stretch C compilers, an instruction-set simulator, a profiler, and a debugger.

Stretch Inc.
www.stretchinc.com

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