Electronic Design

The ISSCC Sets The Tone For Twenty-First Century ICs

While the IEDM is a harbinger of device and process advances, the ISSCC is a precursor to cutting-edge IC designs that exploit the latest developments in transistor structures and fabrication technologies. ISSCC 2000, which starts this week at the San Francisco Marriott Hotel, maintains that tradition.

This conference should break new ground and report on several major developments for the first time, as designers from around the world convene to disclose their achievements in analog, digital, and mixed-signal ICs using state-of-the-art deep-submicron and other exotic processes. In fact, as they unveil their vision of emerging chips, this global forum will push system-level integration closer to reality. It also will set the stage for a new generation of system-on-a-chip (SoC) solutions incorporating novel architectures and intellectual properties (IPs) to address emerging applications that were hitherto impractical.

Key developments to watch include a 40-Gbit/s OC-768 chip set comprising a preamplifier with a 45-GHz bandwidth and 32-dB gain, and a four-channel high-sensitivity demultiplexer incorporating a decision circuit using SiGe HBTs. Other advances include a 60-MHz MPEG-4 video-phone SoC solution with 16 Mbits of embedded DRAM, and a 4-Mbit non-volatile ferroelectric RAM.

Furthermore, designers will present a 10.7-MHz switched capacitor IF filter with greater than 35-dB variable gain and a center frequency accuracy within 0.024%, and a CMOS analog front end for mega-pixel camcorders. Look out for refrigeration technologies for sub-ambient operation of CMOS circuits, and a first-generation IA-64 microprocessor with 25.4 million transistors on a single chip, too.

Besides unwrapping gigahertz 64-bit processors in the digital arena, the forum also sheds new light on data converter chips. A session on oversampling converters demonstrates the feasibility of constructing 16-bit 2.5-MHz output-rate analog-to-digital converters (ADCs) with 95-dB signal-to-noise ratio and 102-dB spurious-free dynamic range.

Analog techniques will be highlighted in a paper on an interpolated parallel 6-bit 800-Msample/s ADC based on 0.25-µm CMOS. Those interested in communications will get a first-hand look at a fully integrated SiGe receiver chip for 10-Gbit/s SONET applications, a complete zero-IF or direct-conversion DECT biCMOS transceiver, and an integrated CMOS analog front end with variable data rates for HDSL2 applications.

The conference points toward interesting technology trends, as well. A receiver chip with an integrated linear dipole antenna for on-chip wireless interconnection signals the possibility of inter- and intra-chip wireless links. Also, an ultra-low-power programmable DSP requiring only 560 nW at 1.5 V is powered by a MEMS transducer that converts vibrations to electric energy.

Keeping with its theme, the ISSCC will kick off with a plenary talk on 21st century cars and ICs by Toyota Motor's Naoki Noda. This speech will focus on technological innovations in the auto industry, emphasizing the role of semiconductors in this revolution. Certainly, the amount of electronics and semiconductors implemented in cars is increasing at an amazing rate, evolving toward an intelligent transportation system.

Two other invited experts are Guenter Weinberger of Infineon Technologies and Mark Pinto of Lucent Technologies. Weinberger investigates underlying technologies to realize a true mobile society for the new millennium. Pinto explores forces driving system-level integration in ICs. And, evening panel sessions chart the course for ICs in the 21st century.

TAGS: Digital ICs
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