Instruction- and cycle-accurate simulation models of cores based on MIPS Technologies's MIPS32 and MIPS64 architectures have been added to the company's MaxSim synchronous multi-core simulation environment. The core models allow system integrators using MIPS-based embedded processor cores to verify their designs. The models can be combined with a variety of DSP and/or other core models found in the environment's library, which includes cores from DSP Group, Infineon, LSI Logic, Conexant and others. The MaxSim library is designed to deliver high-speed, C/C++-based simulation of multi-core systems-on-a-chip (SoCs), as well as enable synchronous debugging of the SoCs. For other details and information about licensing, contact AXYS DESIGN AUTOMATION INC., Palo Alto, CA. (650) 526-1403.