Electronic Design

MIPS-Laden Processors Hit The Road Running

Packing high-performance compute engines and plenty of peripheral support features, two new processors meet the increasingly voracious demands of telematics.

Over the past decade, the amount of in-cabin electronic systems in a car has exploded. Due to cost concerns, many telematics systems have been added like patches in a quilt, each containing a low-cost processor, memory, communications interface, and other functions. Yet as applications are added, more MIPS are needed to perform all required computations. Distributing MIPS across a large number of individual processors significantly duplicates silicon resources. A processor with enough horsepower at the right price-point could eliminate such resources.

Further, if a single processor coordinated all of the functions, each could be more aware of what's happening with the other functions. Once that occurs, smarter vehicles that provide more integrated safety features could get on the road, eliminating accidents and injuries.

To handle the myriad applications found in the latest cars, processors that can deliver compute throughputs of many hundreds of MIPS are needed. These processors also must be able to communicate with the automotive buses/networks, perform control and signal processing functions, and allow software upgrades that will permit features to be upgraded or added over the life of the vehicle.

The high throughput can be implemented via a DSP that includes control-oriented instructions or through a high-performance microprocessor with some signal-processing capabilities. Two recent introductions of telematics-oriented processors, one from DSP roots and the other from a general-purpose RISC upbringing, demonstrate the two approaches to the compute challenge.

Analog Devices' second-generation Blackfin DSP provides telematics system designers with a low-power (300 mW) processor that runs at up to 600 MHz (see "Analog Devices DF-53x Blackfin DSP," p. 38). When running at 600 MHz, the top-of-the-line ADSP-BF533 can execute 1200 million multiply-accumulates (MACs) and over 500 million instructions/s.

Still, this processor won't cost a bundle. The BF533 is just $19.95 each in 10,000-unit lots. At its heart is a 16/32-bit integer processor, 148 kbytes of on-chip SRAM, a 16-kbyte instruction cache, and a 32-kbyte data cache. Lower clock-speed versions with less on-chip memory, also available, drop the cost to as little as $4.95 each in 10,000-unit lots.

Coming from DSP roots, the Blackfin has software support in place to handle applications such as speech recognition, echo cancellation/noise reduction, audio (MP3 decoding/encoding, windows media audio decoding), global-positioning, and Bluetooth baseband operations.

The software telematics platform developed around the Blackfin DSP includes a royalty-free real-time operating system, documented communication protocol between the Blackfin and a possible host processor, documented application programming interfaces for application classes, and various drivers.

Though the Blackfin DSP chips aren't designed specifically for telematics systems, they offer many features that match up to the system needs. But for applications that require a more optimized solution, designers at Motorola crafted the MPC5200, a PowerPC-based RISC CPU with a highly integrated set of on-chip resources for telematics applications that can deliver a throughput of 760 Dhrystone 2.1 MIPS (see "Motorola MPC5200," p. 38).

The Motorola solution provides a different mix of on-chip resources versus those on the Blackfin DSP. The MPC5200 includes a pair of control-area-network (CAN 2.0) ports to communicate with in-vehicle control systems, a 10/100BaseT Ethernet media access controller, an AC'97 audio codec interface, a pair of USB 1.1 serial ports, two I2C serial ports, an integrated-development-environment disk-drive interface, and a PCI 2.2 bus master interface. A J1850 class B byte data link controller for low-speed serial data communications is incorporated as well.

The superscalar architecture of the 32-bit PowerPC603e core is supported by 16-kbyte instruction and data caches, a double-precision floating-point unit, and a memory controller that can address up to 256 Mbytes of off-chip DRAM (SDR or DDR). Even with all of these resources, though, the processor won't generate a lot of heat. When clocked at 400 MHz, it consumes just 850 mW. It's also easy on the budget, costing just $22.50 in lots of 10,000 units.

See associated figure

Analog Devices Inc.
www.analog.com

Motorola Inc.
www.motorola.com/semiconductors



Analog Devices BF-53x Blackfin DSP

SYSTEM SPECIFICATIONS
Processor 300-600MHz Blackfin (static operation) DSP with RISC-like architecture
16k instruction/32k data caches
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
Instruction and Data MMU
On-chip PLL capable of 1x to 63x frequency multiplication
Memory 52 kbytes to 148 kbytes on-chip memory, 16 kbytes on-chip SRAM
128 Mbytes of SDRAM off-chip memory
Glueless support for SDRAM, SRAM, flash, ROM
Two dual-channel memory DMA controllers
I/O 12-channel DMA controller
Two dual-channel, full-duplex synchronous serial ports supporting 8 stereo I2S channels
Parallel peripheral interface (PPI)/GPIO, supporting ITU-R 656 video data formats
SPI-compatible port
Three timer/counters with PWM support
UART with IrDA support
Debug JTAG (IEEE 1149.1 test access port)
Packaging 160-pin mini ball grid array (mBGA)
176-lead LQFP
Extended temperature range: −40°C to 85°C


Motorola MPC5200

SYSTEM SPECIFICATIONS
Processor 400-MHz MPC603e (static operation) superscalar architecture
16-kbyte instruction/16-kbyte data caches
Double-precision FPU
Instruction and data MMU
Memory 133/266-MHz SDR/DDR
256-Mbyte, 32-bit data bus
ROM/RAM/flash nonmultiplexed 8/16/32-bit bus
I/O BestComm virtual DMA controller with 16 kbytes of SRAM
Programmable serial controllers with I2S master or slave, Bluetooth, CODEC AC'97 support
Dual 520-kbit/s I2C
Serial peripheral interface (SPI) controller
10/100BaseT Ethernet
Dual-port USB 1.1 master
Dual 1-Mbit/s MSCAN 2.0 A/B controllers
Byte Data Link Controller (BDLC) supports J1850 and 4x mode
56 general-purpose I/O, 2 with wakeup support, 8 with PWM support
Debug JTAG (IEEE 1149.1 test access port)
Common On-Chip Processor (COP) debug port
Packaging 272-pin plastic ball grid array (PBGA)
Extended temperature range: −40°C to 105°C


Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish