Multicore DSP Hits 10 GHz With Fixed And Floating Point Support

Nov. 9, 2010
Texas Instruments TMX320C66x multicore DSP delivers 10 GHz of performance using fixed or floating point algorithms. An SoC version targets LTE wireless based stations.

TMX320C66x block diagram

TMX320C66x family

TMX320C6616 block diagram

Texas Instruments' (TI) TMX320C66x DSP utilizes the new KeyStone multicore architecture. The architecture (Fig. 1) is designed to maximize throughput by distributing work to computation elements within the chip. The Multicore Navigator hardware allows direct communication between cores and memory using TI's TeraNet switch fabric. The Multicore Navigator includes packet aware DMA support and more than 8,000 queues for message management. It is designed to make task scheduling and management significantly easier and faster.

The family C66xx (Fig. 2) consists of three pin-compatible two, four and eight 1.26 GHz core versions, the TMS320C6672, TMS320C6674 and TMS320C6678 respectively. The four core TMS320C6670 system-on-chip (SoC) targets communications applications with the addition of FFT and FEC coprocessors. The TMS320C6616 (Fig. 3) is similar to the TMS320C6670. It is designed for the wireless base station market and foregoes the PCI Express interface and adds AIF 2 antenna interface support. All of the chips include TI's Hyperlink interconnect for linking multiple TI DSPs together.

The DSPs employ fixed and floating point ALUs so developers can now choose the most appropriate methodology. This allows a mixture of applications to run on a system such as robotics or medical imaging where image processing may employ floating point image processing algorithms and fixed point control applications.

The combined cores deliver 10 GHz DSP performance with 320 GMACs and 160 GFLOPs of combined fixed and floating point performance. The TMS320C6616 and TMS320C6670 have 1 Mbytes of L2 cache/core and a shared 2 Mbyte L2 cache managed by the Multicore Shared Memory Controller (MSMC). The other chips have 512 Kbytes of L2 cache/core and 4 Mbytes of shared L2 cache. All have DDR3 memory controllers.

The KeyStone memory architecture also provides an advanced protection mechinism based on privilege IDs. This control spans local memory, cache and external memory for uniform access and protection. The enhanced DMA (EDMA) controllers automatically inheret the ID associated with the device that configures the EDMA.

The memory protection support is suitable for high level operating systems such as Linux. Cores can also run applications only or other low overhead, high performance RTOSes can be employed as well. This range of operting system support is key with chips like the TMS320C6616 that may be the sole compute element within a system.

Communication is key to the family's succcess. There is an on-chip Gigabit Ethernet switch in addition to two Gigabit Ethernet ports. Serial RapidIO (x4) provides additional system connectivity and developers can turn to the Hyperlink ports for tying TI DSPs together. The Hyperlink interfaces provide high speed (12.5 Gbits/s/lane), low overhead connections between DSPs. This is the same kind of interface on-chip so a two chip TMS320C6678 system has essentially 16 cores from a programming perspective. The chips also have TSIP, I2C, UARTs and PCI Express Gen 2 interfaces.

Power management is based on TI’s SmartReflex technology. Developers can also dynamically adjust supply voltages. The chips consume less than 10W when running at 1 GHz. Industrial and extended temperature range versions are available.

The TMS320C6616 includes a network coprocessor with Layer 2 and 3 hardware acceleration. The Layer 2 hardware includes FFT/DFT and Viterbi decoder support commonly used in wireless basestation software. The chip is also designed to support Wideband Code Division Multiple Access – High-Speed Packet Access (WCDMA-HSPA), WCDMA-HSPA+ and Long Term Evolution (LTE). All this allows the TMS320C6616 to handle everything from the digital radio front end to the wired Gigabit Ethernet network.

Development EVM modules start at $399. The EVMs include the multicore software development kit (MC-SDK), Code Composer Studio software and suite of demo application. The software supports a range of proprietary, open source and third party tools including support for Linux. A Windows debug interface is also available. Developers can also take advantage of TI's Embedded Processor Software Toolkit that has tools for applications such as ultrasound processing and medical diagnostics. The C667x pricing starts at $99.

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