At last month’s Fabless Semiconductor Association (FSA) Awards (the FSA is now the Global Semiconductor Association, or GSA), Gordon Campbell, recipient of the Dr. Morris Chang Exemplary Leadership Award, made an interesting observation.
He pointed out that while early transistor radios ranged from two to 10 transistors, an incredibly low total compared to today’s ICs, some of those transistors weren’t actually being used. He then indicated that today’s chips have so many transistors, counting them isn’t worth the effort.
But just to throw out a number, at 45 nm, Intel’s dualcore Penryn chips have 820 million transistors at a die size of 107 mm2. That’s roughly 5 billion transistors per square inch for a chip comprising both logic and memory.
Reduced package sizes and pin pitch, multichip packages, stacked dies, and other packaging improvements also will help digital semiconductors shrink in all dimensions. You’ll see this trend apply to memory, FPGAs, SoCs, DSPs, MCUs, video, audio, and so on.
With all of this silicon area, semiconductor mansions can be built. As a result, FPGAs will steal sockets from DSPs, MCUs, ASSPs, and ASICs. Likewise, flash memory will steal from magnetic storage, and DRAM will steal from SRAM.
And according to market analyst iSuppli Corp., expect the semiconductor market’s revenue to rise 9%, memory to grow 12%, and FPGAs and other logic ICs to balloon by 9% (see the table).
Vendors will start to deploy FPGAs utilizing 45-nm process technology this year, which means devices with half a million lookup tables (LUTs) is a feasible goal. They will also offer a bevy of high-speed SERDES protocols. This combination, along with microprocessor and DSP cores, and onchip memory, allow FPGAs to be promoted to SoCs, which comes standard with a parking space that was once occupied by multiple ICs. They will also offer faster cores, lower-power devices, and better tooling to enable penetration into spaces such as high-performance computing systems.
The terms defining this year’s microcontrollers will be smaller size, more power efficiency, multiple cores, and virtualization. On-chip security will become more ubiquitous as vendors scramble to add networking and wireless connectivity. DSPs will also follow these trends. For a complete discussion on why the industry is incorporating additional cores, virtualization guidelines, and multiprocessing in general, see “Multicore Projects Mean Multiple Choices” at www.electronicdesign.com, ED Online 17695.
For NAND memory in particular, not only will process technologies be shrinking, but companies also will start to move from 1 and 2 bits per cell to 3 and 4 bits. And though DDR3 technology is getting a big push from companies like Intel this year, don’t expect it to become a major player until next year. Memory vendors will be restrategizing their price points, inventory, and processes as well.
“With 2007 ending with considerable price pressure in DRAMs and NAND flash, the first order of business for memory makers will be to get their costs down, by ramping their 70-nm DRAM processes, then moving quickly to their ~55-nm designs,” says Joseph Unsworth, principal analyst of NAND Flash Semiconductors for market analyst Gartner Research. “For NAND, the cost-control directive is the same: ramp 50- to 55-nm NAND processes, and then move quickly to the 40- to 45-nm node.”