Optimized DSPs Target Broadband Infrastructure And Imaging Applications

April 2, 2001
Wrapping memory, peripherals, and interfaces around its powerful second-generation C64x C6000 core, Texas Instruments has generated three DSPs for broadband wireless infrastructure and high-performance imaging/video applications. Offering full...

Wrapping memory, peripherals, and interfaces around its powerful second-generation C64x C6000 core, Texas Instruments has generated three DSPs for broadband wireless infrastructure and high-performance imaging/video applications. Offering full object-code compatibility with the first-generation C62x-based devices, a complete high-level language development environment fully supports the C64x family.

All three DSPs boast a two-level cache memory system incorporating 16 kbytes of level-1 data cache and 16 kbytes of program cache, as well as a 1024-kbyte level-2 unified data and program memory space. For flexibility, 256 kbytes of level 2 can be used as a second level of cache. Other features include a 64-channel enhanced DMA controller, two 133-MHz enhanced memory interfaces, up to three multichannel buffered serial ports, a 32-bit host port interface, standard audio interfaces, and three timers.

While the C6414 offers general-purpose interfaces, the C6415 adds interfaces for network connectivity. The C6415 and C6416 provide additional communication-specific peripherals, such as a 32-bit PCI bus interface for host computers, and a Utopia 2 ATM interface for wide-area network connectivity. The C6416 is the only member that has on-chip coprocessors. And by comparison, TI says the family consumes a third of the power needed to drive the previous generation.

The C6416 is the first C6000 DSP to include two coprocessors optimized for 3G wireless base stations. While the turbo coprocessor enables turbo decoding on voice channels, the Viterbi coprocessor performs convolution decoding of voice channels. By combining the core and coprocessors, the C6416 can support symbol-rate processing of over 300 AMR voice channels at 12.2 kbits/s and 35 data channels at 384 kbits/s.

Sampling is scheduled to begin in June. The first 0.12-µm CMOS DSPs will operate at up to 600 MHz. The three DSPs will come in 400-, 500-, and 600-MHz versions and will be offered in 532-lead BGA packages. The C64x core, scalable to 1.1 GHz, supports multicore designs. In 10,000-piece quantities, the 400-MHz C6414 costs $95.

Texas Instruments, 12500 TI Blvd., Dallas, TX 75243-4136; (800) 336-5236; www.dspvillge.ti.com/newc64xdsps.

See associated figure.

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